Abstract
Hierarchical parallel computing is rapidly becoming ubiquitous in high performance computing (HPC) systems. Programming models used commonly in turbomachinery and other engineering simulation codes have traditionally relied upon distributed memory parallelism with MPI and have ignored thread and data parallelism. This paper presents methods for programming multi-block codes for concurrent computational on host multicore CPUs and many-core accelerators such as graphics processing units. Portable and standardized methods are language directives that are used to expose data and thread parallelism within the hybrid shared and distributed-memory simulation system. A single-source/multiple-object strategy is used to simplify code management and allow for heterogeneous computing. Automated load balancing is implemented to determine what portions of the domain are computed by the multi-core CPUs and GPUs. Preliminary results indicate that a moderate overall speed-up is possible by taking advantage of all processors and accelerators on a given HPC node.
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Notes
- 1.
This assumes that all operations can be computed within a vector logic unit capable of processing eight values simultaneously compared to a scalar logic unit.
- 2.
The legacy !dir$ ivdep directive can often be used where OpenMP v4 is not supported.
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Acknowledgements
This material is based upon work supported by, or in part by, the Department of Defense High Performance Computing Modernization Program (HPCMP) under User Productivity, Technology Transfer and Training (PETTT) contract number GS04T09DBC0017.
US Department of Defense (DoD) Distribution Statement A: Approved for public release. Distribution is unlimited.
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Stone, C.P., Davis, R.L., Lee, D.Y. (2018). Concurrent Parallel Processing on Graphics and Multicore Processors with OpenACC and OpenMP. In: Chandrasekaran, S., Juckeland, G. (eds) Accelerator Programming Using Directives. WACCPD 2017. Lecture Notes in Computer Science(), vol 10732. Springer, Cham. https://doi.org/10.1007/978-3-319-74896-2_6
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