Abstract
System-on-chips (SoCs) incorporate a multitude of analog and digital circuit blocks with complex functionalities into a single chip. Verification of SoC designs is a humongous task executed by a large team over the course of a few months’ time frame. Prior to integration of each block to the SoC fabric, which is usually controlled by a processor, the block needs to be thoroughly verified for its functionality. Toward this, methodologies like Universal Verification Methodology (UVM) have enabled verification engineers to verify such complex designs with relative ease. While detailed verification of the individual modules is possible at the unit level, verification of all functionalities at the top level still remains a challenge. The limited number of tests run at SoC level is dwarfed by the large number of tests performed at unit levels. This is primarily due to the processor being driven by a software stimulus, while the unit tests with constrained-random verification are written as System Verilog UVM sequences. The real deficit comes when testing the manufactured device against functional specifications due to lack of sufficient tests for individual blocks. Achieving complete functional testing of SoC device is impossible without covering the verification space exercised by the stand-alone tests at unit level. In this paper, we propose a method to utilize the stand-alone functional test scenarios verified at unit level, by converting these scenarios into top-level functional tests that can be used to derive functional test vectors for testing the SoC device. Including these unit-level test scenarios into the top-level functional vectors increases the confidence on the device for its total functionality.
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Anilkumar, R., Varaprasad, B.K.S.V.L., Padmapriya, K. (2022). Automation of Translating Unit-Level Verification Scenarios for Test Vector Generation of SoC. In: Nagar, A.K., Jat, D.S., Marín-Raventós, G., Mishra, D.K. (eds) Intelligent Sustainable Systems. Lecture Notes in Networks and Systems, vol 333. Springer, Singapore. https://doi.org/10.1007/978-981-16-6309-3_50
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DOI: https://doi.org/10.1007/978-981-16-6309-3_50
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