[go: up one dir, main page]
More Web Proxy on the site http://driver.im/ Skip to main content

Advertisement

Springer Nature Link
Log in

An Improved Harmony Search Approach for Block Placement for VLSI Design Automation

  • Published:
Wireless Personal Communications Aims and scope Submit manuscript

Abstract

Level of knowledge with the field for VLSI IC Design’s Placement and Routing and in the area of Wireless Communication is rapidly evolving; Hence the process designing in the above fields is critical to assimilate a higher quantity of computation elements or nodes into a very compact size in VLSI Area and also the same is applicable in Wireless Communications to cover more number of nodes in a specific area. Prior to completing the placement, the physical and technical arranging of the computation elements or nodes in the chip area is planned, which is nothing more than Placement step and analogous with coverage of nodes in Wireless communication. Floorplanning must be done properly for reduce given placement area in physical ICDie. The proposed work suggests an ImprovisedHarmonySearch-IHS Optimization Algorithm, which is an Sequential combination of the HarmonySearch (HS) Algorithm and the most effective Particle Swarm Optimization (PSO) Algorithm to achieve the major objective of the VLSI Placement approach and applicable to the field of Wireless Communication. The aim at this point is to reduce the gap between the standard area of the benchmark circuit to the obtained area of the corresponding benchmark circuit. The MATLAB code for the ImprovisedHarmonySearch-IHS Algorithm is recreated, and discoveries are tested for better inspection using standard MCNC, or North Carolina Microelectronics Center benchmark circuits and suggest to adopt the corresponding results to the area of Wireless communication.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Log in via an institution

Subscribe and save

Springer+ Basic
£29.99 /Month
  • Get 10 units per month
  • Download Article/Chapter or eBook
  • 1 Unit = 1 Article or 1 Chapter
  • Cancel anytime
Subscribe now

Buy Now

Price includes VAT (United Kingdom)

Instant access to the full article PDF.

Institutional subscriptions

Fig. 1
Fig. 2
Fig. 3
Fig. 4
Fig. 5
Fig. 6
Fig. 7
Fig. 8
Fig. 9
Fig. 10
Fig. 11

Similar content being viewed by others

Data Availability

The data that support the findings of this study are available on request from the corresponding author. The data are not publicly available due to containing information that could compromise the privacy of research participants.

Code Availability

The code that support the findings of this study are available on request from the corresponding author. The codes are not publicly available due to containing information that could compromise the privacy of research participants.

References

  1. Chandrasekaran, G., Periyasamy, S., & Rajamanickam, K. P. (2019). Minimization of test time in system on chip using artificial intelligence-based test scheduling techniques. Neural Computing and Applications,1–10

  2. Wu, C., Fang, J., & Li, Q. (2019). Multi-material topology optimization for thermal buckling criteria. Computer Methods in Applied Mechanics and Engineering, 346, 1136–1155

    Article  MathSciNet  MATH  Google Scholar 

  3. Sivasubramanian, K., & Jayanthi, K. B. (2015). Music-inspired harmony search algorithm for fixed outline non-slicing VLSI floorplanning. World Academy of Science, Engineering and Technology, International Journal of Electrical, Computer, Energetic, Electronic and Communication Engineering, 9(6), 512–519

  4. Gwee, B. H., & Lim, M. H. (1999). A GA with heuristic-based decoder for IC floorplanning. Integration, 28(2), 157–172

    Article  Google Scholar 

  5. Shaik Karimullah, & D. Vishnu Vardhan (2022). Pin density technique for congestion estimation and reduction of optimized design during placement and routing. Applied Nanoscience.

  6. Fernando, P. R. (2009). Genetic algorithm based design and optimization of VLSI ASICs and reconfigurable hardware

  7. Grefenstette, J., Gopal, R., Rosmaita, B., & Van Gucht, D. (1985, July). Genetic algorithms for the traveling salesman problem. In Proceedings of the first International Conference on Genetic Algorithms and their Applications (Vol. 160, No. 168, pp. 160–168). Lawrence Erlbaum

  8. Karimullah, S., & Vishnuvardhan, D. (2018) A review paper on optimization of placement and routing techniques. International Journal of Engineering and Techniques.

  9. Rebaudengo, M., & Reorda, M. S. (1996). GALLO: A genetic algorithm for floorplan area optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 15(8), 943–951

    Article  Google Scholar 

  10. Venkatraman, S., & Sundhararajan, M. (2017). Optimization of VLSI floorplanning using genetic algorithm. J Chem Pharm Sci JCPS, 10(1), 311–316

    Google Scholar 

  11. Karimullah, S., Vardhan, D. V., & Basha, S. J. (2020). Floorplanning for Placement of Modules in VLSI Physical Design Using Harmony Search Technique. ICDSMLA 2019 (pp. 1929–1936). Singapore: Springer

    Chapter  Google Scholar 

  12. Yang, X. S. (2010). Biology-derived algorithms in engineering optimization. arXiv preprint arXiv:1003.1888

  13. Funke, J., Hougardy, S., & Schneider, J. (2016). An exact algorithm for wirelength optimal placements in VLSI design. Integration, 52, 355–366

    Article  Google Scholar 

  14. Kureychik, V., & Kulakov, A. (2017, December). Algorithm of Thermal Optimization of Placement of Basic Elements of VLSI. In IV International research conference” Information technologies in Science, Management, Social sphere and Medicine (ITSMSSM 2017). Atlantis Press

  15. Chandrasekaran, G., Periyasamy, S., & Karthikeyan, P. R. (2019). Test scheduling for system on chip using modified firefly and modified ABC algorithms. SN Applied Sciences, 1(9), 1079

    Article  Google Scholar 

  16. Shaik Karimullah, S. J., Basha, P., Guruvyshnavi, K., & Sathish Kumar Reddy (2020). B Navyatha ”A Genetic Algorithm with Fixed Open Approach for Placements and Routings” ICCCE (pp. 599–610). Publisher Springer

  17. Vishnuvardhan, D. D., Shaik Karimullah” Monitering Physiological Variables Of Mining Workers” Ncetimes#1.0, Ijet Issn:2395-1303-2018

  18. Jeevitheswari, B., S. Karimullah, Vishnu Vardhan (2017). A Low Power DFT Based CMOS Receiver with Dual Use of Power Lines” IJSETR 6(22), 4470–4475

  19. venkatraman, S., & Sundhararajan, M. (2017). Particle Swarm Optimization Algorithm For VLSI Floorplanning Problem. J Chem Pharm Sci Jcps, 10(1), 311–316

    Google Scholar 

  20. Xue, B., Zhang, M., & Browne, W. N. (2012). Particle swarm optimization for feature selection in classification: A multi-objective approach. IEEE transactions on cybernetics, 43(6), 1656–1671

    Article  Google Scholar 

  21. Maji, K. B., Ghosh, A., Kar, R., Mandal, D., & Ghoshal, S. P. (2015, November). An evolutionary algorithm based approach for VLSI floor-planning. In 2015 International Conference on Science and Technology (TICST) (pp. 248–253). IEEE

  22. Laudis, L. L., Shyam, S., Jemila, C., & Suresh, V. (2018). MOBA: multi objective bat algorithm for combinatorial optimization in VLSI. Procedia Computer Science, 125, 840–846

    Article  Google Scholar 

  23. Basir-Kazeruni, S., Yu, H., Gong, F., Hu, Y., Liu, C., & He, L. (2013). SPECO: Stochastic Perturbation based Clock tree Optimization considering temperature uncertainty. Integration, 46(1), 22–32

    Article  Google Scholar 

  24. Yang, P., Yang, H., Qiu, W., Wang, S., & Li, C. (2014). Optimal approach on net routing for VLSI physical design based on Tabu-ant colonies modeling. Applied Soft Computing, 21, 376–381

    Article  Google Scholar 

  25. Ghosh, S., & Samanta, S. (2014). Fixed structure compensator design using a constrained hybrid evolutionary optimization approach. ISA transactions, 53(4), 1119–1130

    Article  Google Scholar 

  26. Karimullah, S., & Vishnuvardhan, D. (2020). Iterative Analysis of Optimization Algotithms for Placement and Routing in Asic Design. ICDSMLA 2019 (pp. 1947–1958). Singapore: Springer

    Chapter  Google Scholar 

  27. Kourany, T., Ghoneima, M., Hegazi, E., & Ismail, Y. (2017). Passiot: a pareto-optimal multi-objective optimization approach for synthesis of analog circuits using sobol’indices-based engine. Integration, 58, 9–21

    Article  Google Scholar 

  28. Chen, J., Liu, Y., Zhu, Z., & Zhu, W. (2017). An adaptive hybrid memetic algorithm for thermal-aware non-slicing VLSI floorplanning. Integration, 58, 245–252

    Article  Google Scholar 

  29. Sivaranjani, P., & Kumar, A. S. (2015). Thermal-aware non-slicing VLSI floorplanning using a smart decision-making PSO-GA based hybrid algorithm. Circuits Systems and Signal Processing, 34(11), 3521–3542

    Article  Google Scholar 

  30. Karimullah, S., & Vishnuvardhan, D. (2020). Experimental Analysis of Optimization Techniques for Placement and Routing in ASIC Design. In ICDSMLA 2019 (pp. 908–917). Singapore: Springer

    Google Scholar 

Download references

Funding

None.

Author information

Authors and Affiliations

  1. Jawaharlal Nehru Technological University, Anantapur, A P, India

    Shaik Karimullah

  2. Department of Electronics and Communication Engineering, Jawaharlal Nehru Technological University, Anantapur, A P, India

    D. Vishnuvardhan

  3. Dept. of Electrical and Computer Engineering, San Francisco State University, 94132, San Francisco, CA, USA

    Vidhyacharan Bhaskar

Authors
  1. Shaik Karimullah
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. D. Vishnuvardhan
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. Vidhyacharan Bhaskar
    View author publications

    You can also search for this author in PubMed Google Scholar

Contributions

Shaik Karimullah: Conceptualization, Methodology, Writing - original draft, Analysis. D.Vishnuvardhan: Visualization, Investigation, Validation, Editing, Supervision. Vidhyacharan Bhaskar: Supervision, Writing - review & editing.

Corresponding author

Correspondence to Vidhyacharan Bhaskar.

Ethics declarations

Conflicts of interest/Competing interests

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this paper.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Reprints and permissions

About this article

Check for updates. Verify currency and authenticity via CrossMark

Cite this article

Karimullah, S., Vishnuvardhan, D. & Bhaskar, V. An Improved Harmony Search Approach for Block Placement for VLSI Design Automation. Wireless Pers Commun 127, 3041–3059 (2022). https://doi.org/10.1007/s11277-022-09909-2

Download citation

  • Received:

  • Revised:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s11277-022-09909-2

Keywords