Abstract
A voltage-to-time converter (VTC) architecture with high-bandwidth SFDR performance is presented. This VTC circuit is compatible with high-speed, high-bandwidth RF ADC systems. The proposed VTC utilizes the bottom plate sampling of the capacitor. A constant current source charges the capacitor and generates a ramp signal, which passes through the threshold comparator to output the time pulse signal. An independent sampling process RC loop is adopted to improve the input bandwidth of VTC. The circuit architecture of the cascode current source charging directly to the capacitor provides the linearity of the VTC. A novel bootstrapped switch is employed to further improve the linearity of VTC. The prototype VTC was fabricated in a 65 nm CMOS process with an active area of 0.008 mm2. It exhibits an SNR of 62.7 dB and an SFDR of 54.6 dB for an input frequency of 6 GHz and a sampling rate of 500 MS/s under the TT process corner simulation.
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Duan, J., Liu, M., Zhu, Z. et al. A 6.3 GHz high bandwidth voltage-to-time converter with high linearity. Analog Integr Circ Sig Process 100, 663–670 (2019). https://doi.org/10.1007/s10470-019-01503-0
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DOI: https://doi.org/10.1007/s10470-019-01503-0