HyperTransportation

HyperTransportation
bus (en)
Bayanai
Time of discovery or invention (en)	2001
Mai haɓakawa	HyperTransport Consortium (en)

HyperTransport (HT), wanda aka fi sani da Lightning Data Transport, fasaha ce don haɗin gwiwar masu sarrafawa kwamfuta. Yana da nau'i-nau'i na biyu / layi daya mai faɗin layi, haɗin kai-da-ma'auni wanda aka gabatar a ranar 2 ga Afrilu, 2001. Kungiyar HyperTransport Consortium tana da alhakin ingantawa da haɓaka fasahar HyperTransport.

HyperTransport an fi sani da tsarin tsarin bas na AMD na tsakiya (CPUs) daga Athlon 64 ta hanyar AMD FX da kuma chipsets na motherboard da ke hade. IBM da Apple sun yi amfani da HyperTransport don na'urorin Power Mac G5, da kuma tsarin MIPS na zamani.

Bayanan da ke cikin HTX 3.1 na yanzu sun kasance masu gasa don saurin gudu na 2014 (2666 da 3200 MT / s ko kusan 10.4 GB / s da 12.8 GB / s) DDR4 RAM da sannu a hankali (kimanin 1 GB / s [1] kama da babban PCIe SSDs ULLtraDIMM flash RAM) fasahar [haskakawa da ake buƙata] - saurin RAM a kan bas na CPU na yau da kullun fiye da kowane bas na gaba na Intel. Fasahar Intel tana buƙatar kowane saurin RAM don samun nasa dubawa, wanda ke haifar da shimfidar motherboard mai rikitarwa amma tare da ƙananan ƙuntatawa. HTX 3.1 a 26 GB / s na iya aiki a matsayin bas ɗin da aka haɗa don kusan sanduna huɗu na DDR4 da ke gudana a saurin da aka tsara. Bayan wannan DDR4 RAM na iya buƙatar bas biyu ko fiye na HTX 3.1 wanda ke rage darajarta a matsayin jigilar kaya.

HyperTransport ya zo a cikin nau'o'i huɗu - 1.x, 2.0, 3.0, da 3.1 - wanda ke gudana daga 200 MHz zuwa 3.2 GHz.   Har ila yau, haɗin DDR ne ko "ƙididdigar bayanai biyu", ma'ana yana aika bayanai a kan bangarorin tashi da faɗuwa na siginar agogo. Wannan yana ba da damar matsakaicin adadin bayanai na 6400 MT / s yayin gudana a 3.2 GHz.  Ana yin shawarwari da mitar aiki tare da chipset na motherboard (North Bridge) a cikin lissafin yanzu.

HyperTransport yana goyan bayan faɗin bit mai zaman kansa, daga 2 zuwa 32 bits a kowace hanyar haɗi; akwai hanyoyin haɗi guda biyu a kowace bas din HyperTransport.  Tare da zuwan sigar 3.1, ta amfani da cikakkun hanyoyin haɗin 32-bit da amfani da cikakken ƙayyadaddun ƙayyadadden HyperTransport 3.1 na aiki, ƙimar canja wurin ka'idoji shine 25.6 GB / s (3.2 GHz × 2 canja wurin kowane agogo × 32 bit / s da aka tara ta hanyar hanya, ko 51.2 GB / s da ya sa ya fi sauri fiye da mafi yawan ma'aunin bas na yanzu don tashoshin aiki na PC da sabobin da kuma sa ya fi sa ya fi sauƙi fiye da mafi yawancin ma'auni na bas don ƙididdigar aiki da cibiyar sadarwa.    

Za'a iya haɗa haɗin kai na faɗin daban-daban tare a cikin tsarin tsarin tsarin guda ɗaya kamar yadda yake a cikin hanyar haɗi ta 16-bit zuwa wani CPU da hanyar haɗi na 8-bit zuwa na'urar gefe, wanda ke ba da damar haɗin kai tsakanin CPUs, da ƙananan haɗin kai ga kewayon kamar yadda ya dace. Hakanan yana goyan bayan rarraba hanyar haɗi, inda za'a iya raba hanyar haɗi guda 16 zuwa hanyoyin haɗi guda biyu. Fasahar kuma yawanci tana da ƙananan jinkiri fiye da sauran mafita saboda ƙananan kuɗin da take da shi.

Ta hanyar lantarki, HyperTransport yayi kama da siginar bambancin low-voltage (LVDS) da ke aiki a 1.2 V.^[1] HyperTransport 2.0 ya kara da mai watsawa na bayan cursor.  HyperTransport 3.0 ya kara da matsawa da daidaitawar matakin mai karɓa da kuma zaɓi na mai watsawa.

HyperTransport ya dogara ne da fakitin, inda kowane fakiti ya ƙunshi saiti na kalmomi 32-bit, ba tare da la'akari da faɗin jiki na hanyar haɗi ba. Kalmar farko a cikin fakiti koyaushe tana ƙunshe da filin umarni. Kunshin da yawa suna dauke da adireshin 40-bit. Ana buƙatar ƙarin kunshin sarrafa 32-bit lokacin da ake buƙatar adireshin 64-bit. Ana aika kayan aiki na bayanai bayan fakitin sarrafawa. Ana canja wurin koyaushe zuwa nau'i-nau'i na 32 bits, ba tare da la'akari da ainihin tsawon su ba. 

Kunshin HyperTransport sun shiga haɗin kai a cikin ɓangarorin da aka sani da lokutan bit. Yawan lokutan bit da ake buƙata ya dogara da faɗin haɗin. HyperTransport kuma yana tallafawa saƙon sarrafa tsarin, katsewar sigina, bayar da bincike ga na'urorin da ke kusa da su ko masu sarrafawa, ma'amaloli na I / O, da ma'amuran bayanai gaba ɗaya. Akwai nau'ikan umarni biyu na rubuce-rubuce da ake tallafawa: an buga da kuma wadanda ba a buga su ba. Rubuce-rubucen da aka buga ba sa buƙatar amsawa daga manufa. Ana amfani da wannan yawanci don na'urorin bandwidth masu yawa kamar zirga-zirgar damar ƙwaƙwalwar ajiya ko canja wurin damar ƙwaƙwalwa kai tsaye. Rubuce-rubucen da ba a aika su ba suna buƙatar amsa daga mai karɓa a cikin hanyar amsawar "da aka yi manufa". Karanta kuma yana buƙatar amsa, wanda ke dauke da bayanan da aka karanta. HyperTransport yana tallafawa tsarin umarni na PCI mai amfani / mai samarwa.

HyperTransport kuma yana sauƙaƙa Gudanar da wutar lantarki kamar yadda ya dace da ƙayyadaddun Tsarin Ci gaba da Ƙayyadaddwar Wutar. Wannan yana nufin cewa canje-canje a cikin jihohin bacci na processor (C jihohi) na iya nuna canje-canje cikin jihohin na'ura (D jihohi), misali kashe diski lokacin da CPU ya tafi barci. HyperTransport 3.0 ya kara da ƙarin damar don ba da damar mai kula da kula da wutar lantarki don aiwatar da manufofin kula da wutar.

Babban amfani ga HyperTransport shine maye gurbin bas din da aka bayyana a gaban Intel, wanda ya bambanta da kowane nau'in Intel processor. Misali, ba za a iya haɗa Pentium a cikin bas din PCI Express kai tsaye ba, amma dole ne ya fara wucewa ta hanyar adaftan don fadada tsarin. Dole ne bas din da ke gaba ya haɗu ta hanyar masu daidaitawa don bas daban-daban, kamar AGP ko PCI Express. Wadannan galibi ana haɗa su a cikin ayyukan mai kula da su, wato arewacin da kudu.

Sabanin haka, HyperTransport wani bayani ne mai budewa, wanda ƙungiyar kamfanoni da yawa suka buga. Gidan gyaran HyperTransport guda ɗaya zai yi aiki tare da nau'ikan microprocessors masu amfani da HyperTransport.

AMD ta yi amfani da HyperTransport don maye gurbin bas na gaba a cikin Opteron, Athlon 64, Athlon II, Sempron 64, Turion 64, Phenom, Phenom II da FX na iyalan microprocessors.

Wani amfani ga HyperTransport shine a matsayin haɗin kai don kwamfutocin NUMA Multiprocessor. AMD ta yi amfani da HyperTransport tare da tsawo mai zaman kansa a matsayin wani ɓangare na Direct Connect Architecture a cikin Opteron da Athlon 64 FX (Dual Socket Direct Connect (DSDC) Architecture) layin masu sarrafawa. Infinity Fabric da aka yi amfani da shi tare da CPUs na uwar garken EPYC babban tsari ne na HyperTransport. Haɗin HORUS daga Newisys ya faɗaɗa wannan ra'ayi zuwa manyan ɗakunan. Na'urar Aqua daga 3Leaf Systems tana sarrafawa kuma tana haɗa CPUs, ƙwaƙwalwar ajiya, da I / O.

Hakanan ana iya amfani da HyperTransport azaman bas a cikin masu ba da hanya da masu sauyawa. Masu ba da hanya da masu sauyawa suna da hanyoyin sadarwa da yawa, kuma dole ne su tura bayanai tsakanin waɗannan tashoshin jiragen ruwa da sauri. Misali, tashar jiragen ruwa guda huɗu, 1000 Mbit / s Ethernet mai ba da hanya tana buƙatar matsakaicin 8000 Mbit / S na bandwidth na ciki (1000 Mbit / 4 tashar jiragen sama × 2 hanyoyi) - HyperTransport ya wuce bandwidth wannan aikace-aikacen yana buƙata.    Koyaya mai ba da hanya ta 4 + 1 tashar 10 Gb zai buƙaci 100 Gbit / s na bandwidth na ciki.   Ƙara ga wannan 802.11ac 8 antennas da WiGig 60 GHz misali (802.11ad) da HyperTransport ya zama mafi yiwuwa (tare da ko'ina tsakanin 20 da 24 lanes da aka yi amfani da su don bandwidth da ake buƙata). 

Batun jinkiri da bandwidth tsakanin CPUs da co-processors yawanci shine babban toshewa ga aiwatarwa. Co-processors irin su FPGAs sun bayyana wanda zai iya samun damar shiga bas din HyperTransport kuma ya zama hade a kan motherboard. FPGAs na zamani daga manyan masana'antun (Altera da Xilinx) kai tsaye suna tallafawa HyperTransport dubawa, kuma suna da IP Cores samuwa. Kamfanoni irin su XtremeData, Inc. da DRC suna ɗaukar waɗannan FPGAs (Xilinx a cikin yanayin DRC) kuma suna ƙirƙirar tsarin da ke ba da damar FPGAs su shiga kai tsaye cikin Opteron socket.

AMD ta fara wani shiri mai suna Torrenza a ranar 21 ga Satumba, 2006, don ci gaba da inganta amfani da HyperTransport don katunan plug-in da coprocessors. Wannan shirin ya buɗe "Socket F" zuwa allon plug-in kamar waɗanda ke daga XtremeData da DRC.

Wani bayani na haɗin da ke ba da damar kewaye da keɓaɓɓen rami don samun haɗin kai tsaye zuwa microprocessor ta amfani da ƙirar HyperTransport an sake shi ta hanyar HyperTransport Consortium. An san sH da HyperT eX (HTX). Yin amfani da misali mai juyawa na wannan haɗin inji kamar yadda yake da layi 16 na PCI Express (tare da haɗin x1 don fil din wutar lantarki), HTX yana ba da damar ci gaba da katunan plug-in waɗanda ke tallafawa damar kai tsaye ga CPU da DMA zuwa tsarin RAM. Katin farko don wannan rami shine QLogic InfiniPath InfiniBand HCA. IBM da HP, da sauransu, sun saki tsarin da ya dace da HTX.

Matsayin HTX na asali yana iyakance zuwa 16 bits da 800 MHz.^[2]  

A watan Agustan shekara ta 2008, HyperTransport Consortium ta fitar da HTX3, wanda ke fadada sa'ar HTX zuwa 2.6 GHz (5.2 GT / s, 10.7 GTi, 5.2 real GHz data rate, 3 MT / s gyara rate) kuma yana riƙe da baya jituwa.^[3]    

An bayyana haɗin gwajin "DUT" ^[4] don ba da damar daidaita tsarin gwajin aiki.

• AMD AMD64 da Direct Connect Architecture tushen CPUs
• chipsets na AMD
  • Jerin AMD-8000
  • AMD jerin 480
  • AMD jerin 580
  • AMD jerin 690
  • Jerin AMD 700
  • AMD jerin 800
  • Jerin AMD 900
• chipsets na ATI
  • ATI Radeon Xpress 200 don processor na AMD
  • ATI Radeon Xpress 3200 don processor na AMD
• Broadcom (sa'an nan ServerWorks) HyperTransport SystemI / O masu sarrafawa
  • HT-2000
  • HT-2100
• Cisco QuantumFlow Processors
• ht_tunnel daga aikin OpenCores (lasisi na MPL)
• IBM CPC925 da CPC945 (PowerPC 970 northbridges) chipsets
• Loongson-3 Mai sarrafa MIPS
• Nvidia nForce chipsets
  • nForce Professional MCPs (Media da Communication Processor)
  • nForce 3 jerin
  • nForce 4 jerin
  • jerin nForce 500
  • jerin nForce 600
  • nForce jerin 700
  • jerin nForce 900
• PMC-Sierra RM9000X2 MIPS CPU
• Power Mac G5^[5]
• Masu sarrafa zaren Raza
• SiByte MIPS CPUs daga BroadcomBroadcom
• Transmeta TM8000 Efficeon CPUs
• VIA chipsets K8 jerin

HyperTransportation	Shekara	Max. HT mita	Max. faɗin haɗin kai	Max. jimillar bandwidth (GB / s)
				bi-directional	16-bit mai kai tsaye	32-bit mai kai tsaye*
1.0	2001	800 MHz	32 bit	12.8	3.2	6.4
1.1	2002	800 MHz	32 bit	12.8	3.2	6.4
2.0	2004	1.4 GHz	32 bit	22.4	5.6	11.2
3.0	2006	2.6 GHz	32 bit	41.6	10.4	20.8
3.1	2008	3.2 GHz	32 bit	51.2	12.8	25.6

* AMD Athlon 64, Athlon 64 FX, Athlon 64 X2, Athlon X2, Athhlon II, Phenom, Phenom II, Sempron, Turion jerin kuma daga baya amfani da haɗin HyperTransport guda 16. AMD Athlon 64 FX (1207), Opteron yana amfani da hanyoyin haɗin HyperTransport guda uku na 16-bit. Yawan agogo na yau da kullun don waɗannan hanyoyin haɗin sarrafawa sune 800 MHz zuwa 1 GHz (tsoffin tsarin socket guda ɗaya da yawa akan hanyoyin 754/939/940) da 1.6 GHz zuwa 2.0 GHz (sabon tsarin socket ɗaya akan hanyoyin AM2 + / AM3 - mafi yawan sababbin CPUs ta amfani da 2.0 GHz).      Duk da yake HyperTransport kanta tana iya haɗin haɗin faɗin 32-bit, wannan faɗin a halin yanzu ba a amfani da shi ta kowane mai sarrafa AMD. Wasu chipsets duk da haka ba sa amfani da faɗin 16-bit da masu sarrafawa suka yi amfani da shi. Wadanda suka hada da Nvidia nForce3 150, nForce 3 Pro 150, da kuma ULi M1689 - wanda ke amfani da haɗin HyperTransport na 16-bit amma yana iyakance haɗin HyperTransports zuwa 8 bits. 

There has been some marketing confusion^{[ana buƙatar hujja]} between the use of HT referring to HyperTransport and the later use of HT to refer to Intel's Hyper-Threading feature on some Pentium 4-based and the newer Nehalem and Westmere-based Intel Core microprocessors. Hyper-Threading is officially known as Hyper-Threading Technology (HTT) or HT Technology. Because of this potential for confusion, the HyperTransport Consortium always uses the written-out form: "HyperTransport."

Infinity Fabric (IF) babban sashi ne na HyperTransport wanda AMD ta sanar a cikin 2016 a matsayin haɗin kai don GPUs da CPUs. Hakanan ana iya amfani dashi azaman haɗin kai don sadarwa tsakanin CPUs da GPUs (don Tsarin Tsarin Halitta), tsari da aka sani da Tsarin Ƙarshe. ^{[6] [7][8]} Kamfanin ya ce Infinity Fabric zai karu daga 30 GB / s zuwa 512 GB / s, kuma za a yi amfani da shi a cikin Zen-based CPUs da Vega GPUs waɗanda aka sake su a cikin 2017.  

A kan Zen da Zen + CPUs, ana gudanar da haɗin bayanai na "SDF" a daidai wannan mitar kamar agogon ƙwaƙwalwar DRAM (MEMCLK), yanke shawara da aka yi don cire jinkirin da ya haifar da saurin agogo daban-daban. A sakamakon haka, yin amfani da tsarin RAM mai sauri yana sa duk bas din ya fi sauri. Haɗin suna da faɗin 32-bit, kamar yadda yake a cikin HT, amma ana yin canja wurin 8 a kowane sake zagayowar (128-bit fakiti) idan aka kwatanta da na asali 2. Ana yin canje-canjen lantarki don ingantaccen wutar lantarki.^[9] A kan Zen 2 da Zen 3 CPUs, bas din IF yana kan agogo daban, ko dai a cikin rabo na 1: 1 ko 2: 1 zuwa agogo na DRAM, saboda matsalolin farko na Zen tare da DRAM mai saurin gudu wanda ke shafar saurin IF, sabili da haka kwanciyar hankali na tsarin. An kuma ninka faɗin bas ɗin sau biyu.^[10] A kan Zen 4 da kuma daga baya CPUs, IF bas yana iya gudana a wani asynchronous agogo zuwa DRAM, don ba da damar mafi girma agogo saurin da DDR5 ke iya.^[11]

• Bus din da ke motsawa
• Tashar Fiber
• Bas din da ke gaba
• Intel QuickPath Interconnect
• Jerin ƙididdigar ƙididdiga
• PCI Express
• Rashin sauri
• Kyakkyawan aikiManazarta aa

1. ↑ "Overview" (PDF). HyperTransport Consortium. Archived from the original (PDF) on July 16, 2011.
2. ↑ Emberson, David; Holden, Brian (December 12, 2007). "HTX specification" (PDF). HyperTransport Consortium. p. 4. Archived from the original (PDF) on March 8, 2012. Retrieved January 30, 2008.
3. ↑ Emberson, David (June 25, 2008). "HTX3 specification" (PDF). HyperTransport Consortium. p. 4. Archived from the original (PDF) on March 8, 2012. Retrieved August 17, 2008.
4. ↑ Holden, Brian; Meschke, Mike; Abu-Lebdeh, Ziad; D'Orfani, Renato. "DUT Connector and Test Environment for HyperTransport" (PDF). HyperTransport Consortium (in Turanci). Archived from the original (PDF) on September 3, 2006. Retrieved November 12, 2022.
5. ↑ Apple (25 June 2003). "WWDC 2003 Keynote". YouTube (in Turanci). Archived from the original on July 8, 2012. Retrieved October 16, 2009.
6. ↑ AMD. "AMD_presentation_EPYC". Archived from the original on August 21, 2017. Retrieved May 24, 2017.
7. ↑ Merritt, Rick (December 13, 2016). "AMD Clocks Ryzen at 3.4 GHz+". EE Times (in Turanci). Archived from the original on August 8, 2019. Retrieved January 17, 2017.
8. ↑ Alcorn, Paul (March 5, 2020). "AMD's CPU-to-GPU Infinity Fabric Detailed". Tom's Hardware (in Turanci). Retrieved November 12, 2022.
9. ↑ "Infinity Fabric (IF) - AMD". WikiChip (in Turanci).
10. ↑ Cutress, Ian (June 10, 2019). "AMD Zen 2 Microarchitecture Analysis: Ryzen 3000 and EPYC Rome". AnandTech (in Turanci). Retrieved November 12, 2022.
11. ↑ Killian, Zak (1 September 2022). "AMD Addresses Zen 4 Ryzen 7000 Series Memory Overclocking And Configuration Details". HotHardware (in Turanci). Retrieved 4 April 2024.