Verilog version #19
Comments
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Im working on a spinalHDL port of ztachip.
With spinalHDL, then you can then generate to Verilog
Probably available by year-end.
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From: bittu-digital ***@***.***>
Sent: July 5, 2024 1:32 AM
To: ztachip/ztachip ***@***.***>
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Subject: [ztachip/ztachip] Verilog version (Issue #19)
where can I find the verilog versions of the ztachip as Iam not familiar with the VHDL
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@ztachip, have you considered the much more mainstream SystemVerilog instead of niche SpinalHDL?! With SV Interfaces and Structs, you can have about the same expressiveness as SpinalHDL, i.e higher than current VHDL, but much wider reach and audience. When your sources are in SpinalHDL, Amaranth, PipelineC, or another sidestream HDL, the auto-generated mainstream Verilog is rather unreadable... |
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Im really interested in getting ztachip ported to opensource ASIC tool chain however.
You think opensource ASIC toolchain will support SystemVerilog?
Otherwise the cost for ASIC tool chain will be prohibitively expensive for opensource project.
Actually with spinalHDL, you dont really need to look at the generated Verilog, like when you program in "C", you dont need to look at the generated assembly. At least this is my understanding.
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From: Chili.CHIPS ***@***.***>
Sent: July 5, 2024 8:52 PM
To: ztachip/ztachip ***@***.***>
Cc: ztachip ***@***.***>; Mention ***@***.***>
Subject: Re: [ztachip/ztachip] Verilog version (Issue #19)
@ztachip<https://github.com/ztachip>, have you considered the much more mainstream SystemVerilog instead of niche SpinalHDL?!
With SV Interfaces and Structs, you can have about the same expressiveness as SpinalHDL, i.e higher than current VHDL, but much wider reach and audience.
When your sources are in SpinalHDL, Amaranth, PipelineC, or another sidestream HDL, the auto-generated mainstream Verilog is rather unreadable...
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... just think about it: Now, imagine having to understand and solve DFT, STA, Floorplanning and other PNR issues at the netlist level when your RTL sources are already looking like an obfuscated netlist. All that for a complex design which is pushing the Fmax and LP envelope. If you are thinking of a zero-effort, hands-off, push-button back-end flow, think twice. Given that the entire opensource toolchain is based on Verilog, transition from SystemVerilog to Verilog is more natural and simpler than a jump from anything else to Verilog. Also check CHIPS ALLIANCE Verible Linter (@hzeller is in the best position to further elaborate) along with their 3 RISC-V cores, all written in SV:
lowRISC core is also written in a good, rich command of SystemVerilog, yet processed with opensource tools from over 4 years ago. As for the tapeout, we recommend the IHP free shuttle program... |
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I was hoping more for what openRoad promised with 24 hour turn around chip production , for small design but less than optimized chip design.
https://github.com/The-OpenROAD-Project
I think there is a need for low-end ASIC with easy entry point. So we will be less reliant on "black box" chips that keep getting obsolete and running out of stock.
But I agree that it is better to have support both for people who are looking for performance and for people who just need something fast and cheap.
Your recommendation to start with SystemVerilog and convert to Verilog for low-end design is a very good idea and I'm looking into this option since this will cover both camps.
Thx
…________________________________
From: Chili.CHIPS ***@***.***>
Sent: July 6, 2024 12:28 AM
To: ztachip/ztachip ***@***.***>
Cc: ztachip ***@***.***>; Mention ***@***.***>
Subject: Re: [ztachip/ztachip] Verilog version (Issue #19)
... just think about it: ASIC is way more physical than the FPGA, isn't it?!
Now, imagine having to understand and solve DFT, STA, Floorplanning and other PNR issues at the netlist level when your RTL sources are already looking like an obfuscated netlist. All that for a complex design which is pushing the Fmax and LP envelope. If you are thinking of a zero-effort, hands-off, push-button back-end flow, think twice.
Given that the entire opensource toolchain is based on Verilog, transition from SystemVerilog to Verilog is more natural and simpler than a jump from anything else to Verilog.
Also check CHIPS ALLIANCE Verible<https://github.com/chipsalliance/verible> Linter ***@***.***<https://github.com/hzeller> is in the best position to further elaborate) along with their 3 RISC-V cores, all written in SV:
* https://github.com/chipsalliance/Cores-VeeR-EL2#readme
* https://github.com/chipsalliance/Cores-VeeR-EH2#readme
* https://github.com/chipsalliance/Cores-VeeR-EH1#readme
lowRISC<https://github.com/lowRISC/ibex/tree/d019dccb4b6fb1a580cefabff0391a00bb123ffb/syn> core is also written in a good, rich command of SystemVerilog, yet processed with opensource tools from over 4 years ago.
As for the tapeout, we recommend the IHP<https://ihp-open-ip.readthedocs.io/en/latest/> free shuttle program...
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I managed to convert from VHDL to verilog using GHDL. |
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Thanks for your contribution. I followed the guide at https://github.com/ztachip/ztachip/blob/master/Documentation/Vivado.md, but I encountered numerous errors during the conversion. Here is the log: |
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There is probably a problem with your version of GHDL
I have included my version of GHDL binary in ztachip repo. It should work.
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From: kevinli-hw ***@***.***>
Sent: April 5, 2025 2:01 PM
To: ztachip/ztachip ***@***.***>
Cc: ztachip ***@***.***>; Mention ***@***.***>
Subject: Re: [ztachip/ztachip] Verilog version (Issue #19)
Thanks for your contribution. I followed the guide at https://github.com/ztachip/ztachip/blob/master/Documentation/Vivado.md, but I encountered numerous errors during the conversion. Here is the log:
../../HW/src/soc/soc_base.vhd:30:10: unit "numeric_std" not found in library "ieee" ../../HW/src/config.vhd:9:10: unit "numeric_std" not found in library "ieee" ../../HW/src/ztachip_pkg.vhd:28:10: unit "numeric_std" not found in library "ieee" ../../HW/src/ztachip_pkg.vhd:39:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:41:41: subtype "tid_t" is not visible here ../../HW/src/ztachip_pkg.vhd:269:61: subtype "tid_t" is not visible here ../../HW/src/ztachip_pkg.vhd:328:32: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:330:32: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:332:56: subtype "iregister_t" is not visible here ../../HW/src/ztachip_pkg.vhd:340:30: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:342:54: subtype "iregister_auto_t" is not visible here ../../HW/src/ztachip_pkg.vhd:348:35: subtype "tid_t" is not visible here ../../HW/src/ztachip_pkg.vhd:532:19: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:534:20: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:536:41: subtype "page2_t" is not visible here ../../HW/src/ztachip_pkg.vhd:536:50: no declaration for "to_unsigned" ../../HW/src/ztachip_pkg.vhd:538:41: subtype "page2_t" is not visible here ../../HW/src/ztachip_pkg.vhd:538:50: no declaration for "to_unsigned" ../../HW/src/ztachip_pkg.vhd:540:41: subtype "page2_t" is not visible here ../../HW/src/ztachip_pkg.vhd:540:50: no declaration for "to_unsigned" ../../HW/src/ztachip_pkg.vhd:542:41: subtype "page2_t" is not visible here ../../HW/src/ztachip_pkg.vhd:542:50: no declaration for "to_unsigned" ../../HW/src/ztachip_pkg.vhd:548:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:556:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:562:20: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:568:30: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:570:35: subtype "avalon_bus_page_t" is not visible here ../../HW/src/ztachip_pkg.vhd:570:54: no declaration for "to_unsigned" ../../HW/src/ztachip_pkg.vhd:572:34: subtype "avalon_bus_page_t" is not visible here ../../HW/src/ztachip_pkg.vhd:572:53: no declaration for "to_unsigned" ../../HW/src/ztachip_pkg.vhd:574:34: subtype "avalon_bus_page_t" is not visible here ../../HW/src/ztachip_pkg.vhd:574:53: no declaration for "to_unsigned" ../../HW/src/ztachip_pkg.vhd:576:34: subtype "avalon_bus_page_t" is not visible here ../../HW/src/ztachip_pkg.vhd:576:53: no declaration for "to_unsigned" ../../HW/src/ztachip_pkg.vhd:588:49: subtype "tid_t" is not visible here ../../HW/src/ztachip_pkg.vhd:594:50: subtype "page_t" is not visible here ../../HW/src/ztachip_pkg.vhd:606:59: subtype "avalon_bus_page_t" is not visible here ../../HW/src/ztachip_pkg.vhd:612:35: subtype "cid_t" is not visible here ../../HW/src/ztachip_pkg.vhd:616:42: subtype "cid_t" is not visible here ../../HW/src/ztachip_pkg.vhd:634:21: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:636:46: subtype "vector_t" is not visible here ../../HW/src/ztachip_pkg.vhd:666:23: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:668:24: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:670:38: subtype "burstlen_t" is not visible here ../../HW/src/ztachip_pkg.vhd:672:48: subtype "burstlen_t" is not visible here ../../HW/src/ztachip_pkg.vhd:700:24: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:724:27: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:726:38: subtype "dp_data_type_t" is not visible here ../../HW/src/ztachip_pkg.vhd:728:38: subtype "dp_data_type_t" is not visible here ../../HW/src/ztachip_pkg.vhd:730:52: subtype "dp_data_type_t" is not visible here ../../HW/src/ztachip_pkg.vhd:751:24: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:753:49: subtype "stream_id_t" is not visible here ../../HW/src/ztachip_pkg.vhd:779:14: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:780:20: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:781:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:782:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:783:14: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:784:20: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:785:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:786:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:787:14: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:788:20: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:789:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:790:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:791:14: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:792:20: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:793:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:794:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:795:14: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:796:20: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:797:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:798:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:799:16: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:800:17: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:801:21: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:802:22: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:803:16: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:804:10: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:805:11: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:806:17: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:810:16: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:814:14: subtype "dp_data_type_t" is not visible here ../../HW/src/ztachip_pkg.vhd:815:12: subtype "dp_bus_id_t" is not visible here ../../HW/src/ztachip_pkg.vhd:816:13: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:817:19: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:820:134: subtype "dp_data_type_t" is not visible here ../../HW/src/ztachip_pkg.vhd:830:29: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:836:22: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:837:47: subtype "dp_addr_t" is not visible here ../../HW/src/ztachip_pkg.vhd:838:27: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:839:52: subtype "dp_full_addr_t" is not visible here ../../HW/src/ztachip_pkg.vhd:848:49: subtype "dp_bus_id_t" is not visible here ../../HW/src/ztachip_pkg.vhd:849:25: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:850:50: subtype "dp_counter_t" is not visible here ../../HW/src/ztachip_pkg.vhd:881:24: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:888:28: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:889:35: subtype "dp_config_reg_t" is not visible here ../../HW/src/ztachip_pkg.vhd:890:35: subtype "dp_config_reg_t" is not visible here ../../HW/src/ztachip_pkg.vhd:904:24: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:905:49: subtype "dp_thread_t" is not visible here ../../HW/src/ztachip_pkg.vhd:946:12: subtype "dp_opcode_t" is not visible here ../../HW/src/ztachip_pkg.vhd:950:20: subtype "dp_bus_id_t" is not visible here /usr/bin/ghdl-mcode: error limit reached ../../HW/src/soc/soc_base.vhd:127:23: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:128:22: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:129:23: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:133:21: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:165:23: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:166:22: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:167:23: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:171:21: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:186:23: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:187:22: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:188:23: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:192:21: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:467:17: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:468:17: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:547:32: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:570:32: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:588:32: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:607:43: conversion function or type does not match ../../HW/src/soc/soc_base.vhd:608:42: conversion function or type does not match ../../HW/src/soc/soc_base.vhd:610:41: conversion function or type does not match ../../HW/src/soc/soc_base.vhd:623:43: conversion function or type does not match ../../HW/src/soc/axi/axi_split.vhd:28:10: unit "numeric_std" not found in library "ieee" ../../HW/src/soc/soc_base.vhd:676:43: conversion function or type does not match ../../HW/src/soc/soc_base.vhd:677:42: conversion function or type does not match ../../HW/src/soc/soc_base.vhd:679:41: conversion function or type does not match ../../HW/src/soc/soc_base.vhd:692:43: conversion function or type does not match ../../HW/src/soc/soc_base.vhd:694:43: conversion function or type does not match ../../HW/src/soc/soc_base.vhd:695:42: conversion function or type does not match ../../HW/src/soc/soc_base.vhd:708:41: conversion function or type does not match ../../HW/src/soc/soc_base.vhd:712:43: conversion function or type does not match ../../HW/src/soc/axi/axi_merge.vhd:27:10: unit "numeric_std" not found in library "ieee" ../../HW/src/soc/axi/axi_apb_bridge.vhd:27:10: unit "numeric_std" not found in library "ieee" ../../HW/src/soc/axi/axi_stream_write.vhd:27:10: unit "numeric_std" not found in library "ieee" ../../HW/src/soc/axi/axi_stream_read.vhd:27:10: unit "numeric_std" not found in library "ieee" ../../HW/src/soc/soc_base.vhd:1241:56: object prefix must be an array ../../HW/src/soc/soc_base.vhd:1242:25: object prefix must be an array ../../HW/src/soc/soc_base.vhd:1244:56: object prefix must be an array ../../HW/src/soc/soc_base.vhd:1245:25: object prefix must be an array ../../HW/src/soc/soc_base.vhd:1273:25: can't associate 'arlen' with signal interface "axi_arlen_out" ../../HW/src/soc/soc_base.vhd:1273:25: (type of 'arlen' is an erroneous type) ../../HW/src/ztachip_pkg.vhd:1126:13: (type of signal interface "axi_arlen_out" is an erroneous type) ../../HW/src/top/ztachip.vhd:28:10: unit "numeric_std" not found in library "ieee" ../../HW/src/top/ztachip.vhd:38:49: no declaration for "unsigned" ../../HW/src/top/ztachip.vhd:54:49: no declaration for "unsigned" ../../HW/src/soc/tcm.vhd:28:10: unit "std_logic_textio" not found in library "ieee" ../../HW/src/soc/tcm.vhd:28:10: (use --ieee=synopsys or --std=08 for this non-standard synopsys package) ../../HW/src/soc/tcm.vhd:29:10: unit "numeric_std" not found in library "ieee" ../../HW/src/soc/peripherals/time.vhd:21:10: unit "numeric_std" not found in library "ieee" ../../HW/src/soc/peripherals/gpio.vhd:21:10: unit "numeric_std" not found in library "ieee" ../../HW/src/soc/peripherals/uart.vhd:21:10: unit "numeric_std" not found in library "ieee" ../../HW/src/soc/peripherals/vga.vhd:21:10: unit "numeric_std" not found in library "ieee" ../../HW/src/soc/peripherals/camera.vhd:21:10: unit "numeric_std" not found in library "ieee"
I'm not familiar with the tool GHDL. Does this mean that I missed some configuration when using ./convert.sh, or I should download some library for the script?
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[kevinli-hw]kevinli-hw left a comment (ztachip/ztachip#19)<#19 (comment)>
Thanks for your contribution. I followed the guide at https://github.com/ztachip/ztachip/blob/master/Documentation/Vivado.md, but I encountered numerous errors during the conversion. Here is the log:
../../HW/src/soc/soc_base.vhd:30:10: unit "numeric_std" not found in library "ieee" ../../HW/src/config.vhd:9:10: unit "numeric_std" not found in library "ieee" ../../HW/src/ztachip_pkg.vhd:28:10: unit "numeric_std" not found in library "ieee" ../../HW/src/ztachip_pkg.vhd:39:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:41:41: subtype "tid_t" is not visible here ../../HW/src/ztachip_pkg.vhd:269:61: subtype "tid_t" is not visible here ../../HW/src/ztachip_pkg.vhd:328:32: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:330:32: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:332:56: subtype "iregister_t" is not visible here ../../HW/src/ztachip_pkg.vhd:340:30: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:342:54: subtype "iregister_auto_t" is not visible here ../../HW/src/ztachip_pkg.vhd:348:35: subtype "tid_t" is not visible here ../../HW/src/ztachip_pkg.vhd:532:19: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:534:20: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:536:41: subtype "page2_t" is not visible here ../../HW/src/ztachip_pkg.vhd:536:50: no declaration for "to_unsigned" ../../HW/src/ztachip_pkg.vhd:538:41: subtype "page2_t" is not visible here ../../HW/src/ztachip_pkg.vhd:538:50: no declaration for "to_unsigned" ../../HW/src/ztachip_pkg.vhd:540:41: subtype "page2_t" is not visible here ../../HW/src/ztachip_pkg.vhd:540:50: no declaration for "to_unsigned" ../../HW/src/ztachip_pkg.vhd:542:41: subtype "page2_t" is not visible here ../../HW/src/ztachip_pkg.vhd:542:50: no declaration for "to_unsigned" ../../HW/src/ztachip_pkg.vhd:548:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:556:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:562:20: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:568:30: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:570:35: subtype "avalon_bus_page_t" is not visible here ../../HW/src/ztachip_pkg.vhd:570:54: no declaration for "to_unsigned" ../../HW/src/ztachip_pkg.vhd:572:34: subtype "avalon_bus_page_t" is not visible here ../../HW/src/ztachip_pkg.vhd:572:53: no declaration for "to_unsigned" ../../HW/src/ztachip_pkg.vhd:574:34: subtype "avalon_bus_page_t" is not visible here ../../HW/src/ztachip_pkg.vhd:574:53: no declaration for "to_unsigned" ../../HW/src/ztachip_pkg.vhd:576:34: subtype "avalon_bus_page_t" is not visible here ../../HW/src/ztachip_pkg.vhd:576:53: no declaration for "to_unsigned" ../../HW/src/ztachip_pkg.vhd:588:49: subtype "tid_t" is not visible here ../../HW/src/ztachip_pkg.vhd:594:50: subtype "page_t" is not visible here ../../HW/src/ztachip_pkg.vhd:606:59: subtype "avalon_bus_page_t" is not visible here ../../HW/src/ztachip_pkg.vhd:612:35: subtype "cid_t" is not visible here ../../HW/src/ztachip_pkg.vhd:616:42: subtype "cid_t" is not visible here ../../HW/src/ztachip_pkg.vhd:634:21: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:636:46: subtype "vector_t" is not visible here ../../HW/src/ztachip_pkg.vhd:666:23: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:668:24: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:670:38: subtype "burstlen_t" is not visible here ../../HW/src/ztachip_pkg.vhd:672:48: subtype "burstlen_t" is not visible here ../../HW/src/ztachip_pkg.vhd:700:24: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:724:27: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:726:38: subtype "dp_data_type_t" is not visible here ../../HW/src/ztachip_pkg.vhd:728:38: subtype "dp_data_type_t" is not visible here ../../HW/src/ztachip_pkg.vhd:730:52: subtype "dp_data_type_t" is not visible here ../../HW/src/ztachip_pkg.vhd:751:24: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:753:49: subtype "stream_id_t" is not visible here ../../HW/src/ztachip_pkg.vhd:779:14: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:780:20: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:781:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:782:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:783:14: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:784:20: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:785:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:786:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:787:14: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:788:20: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:789:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:790:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:791:14: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:792:20: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:793:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:794:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:795:14: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:796:20: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:797:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:798:18: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:799:16: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:800:17: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:801:21: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:802:22: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:803:16: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:804:10: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:805:11: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:806:17: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:810:16: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:814:14: subtype "dp_data_type_t" is not visible here ../../HW/src/ztachip_pkg.vhd:815:12: subtype "dp_bus_id_t" is not visible here ../../HW/src/ztachip_pkg.vhd:816:13: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:817:19: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:820:134: subtype "dp_data_type_t" is not visible here ../../HW/src/ztachip_pkg.vhd:830:29: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:836:22: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:837:47: subtype "dp_addr_t" is not visible here ../../HW/src/ztachip_pkg.vhd:838:27: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:839:52: subtype "dp_full_addr_t" is not visible here ../../HW/src/ztachip_pkg.vhd:848:49: subtype "dp_bus_id_t" is not visible here ../../HW/src/ztachip_pkg.vhd:849:25: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:850:50: subtype "dp_counter_t" is not visible here ../../HW/src/ztachip_pkg.vhd:881:24: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:888:28: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:889:35: subtype "dp_config_reg_t" is not visible here ../../HW/src/ztachip_pkg.vhd:890:35: subtype "dp_config_reg_t" is not visible here ../../HW/src/ztachip_pkg.vhd:904:24: no declaration for "unsigned" ../../HW/src/ztachip_pkg.vhd:905:49: subtype "dp_thread_t" is not visible here ../../HW/src/ztachip_pkg.vhd:946:12: subtype "dp_opcode_t" is not visible here ../../HW/src/ztachip_pkg.vhd:950:20: subtype "dp_bus_id_t" is not visible here /usr/bin/ghdl-mcode: error limit reached ../../HW/src/soc/soc_base.vhd:127:23: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:128:22: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:129:23: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:133:21: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:165:23: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:166:22: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:167:23: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:171:21: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:186:23: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:187:22: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:188:23: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:192:21: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:467:17: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:468:17: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:547:32: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:570:32: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:588:32: no declaration for "unsigned" ../../HW/src/soc/soc_base.vhd:607:43: conversion function or type does not match ../../HW/src/soc/soc_base.vhd:608:42: conversion function or type does not match ../../HW/src/soc/soc_base.vhd:610:41: conversion function or type does not match ../../HW/src/soc/soc_base.vhd:623:43: conversion function or type does not match ../../HW/src/soc/axi/axi_split.vhd:28:10: unit "numeric_std" not found in library "ieee" ../../HW/src/soc/soc_base.vhd:676:43: conversion function or type does not match ../../HW/src/soc/soc_base.vhd:677:42: conversion function or type does not match ../../HW/src/soc/soc_base.vhd:679:41: conversion function or type does not match ../../HW/src/soc/soc_base.vhd:692:43: conversion function or type does not match ../../HW/src/soc/soc_base.vhd:694:43: conversion function or type does not match ../../HW/src/soc/soc_base.vhd:695:42: conversion function or type does not match ../../HW/src/soc/soc_base.vhd:708:41: conversion function or type does not match ../../HW/src/soc/soc_base.vhd:712:43: conversion function or type does not match ../../HW/src/soc/axi/axi_merge.vhd:27:10: unit "numeric_std" not found in library "ieee" ../../HW/src/soc/axi/axi_apb_bridge.vhd:27:10: unit "numeric_std" not found in library "ieee" ../../HW/src/soc/axi/axi_stream_write.vhd:27:10: unit "numeric_std" not found in library "ieee" ../../HW/src/soc/axi/axi_stream_read.vhd:27:10: unit "numeric_std" not found in library "ieee" ../../HW/src/soc/soc_base.vhd:1241:56: object prefix must be an array ../../HW/src/soc/soc_base.vhd:1242:25: object prefix must be an array ../../HW/src/soc/soc_base.vhd:1244:56: object prefix must be an array ../../HW/src/soc/soc_base.vhd:1245:25: object prefix must be an array ../../HW/src/soc/soc_base.vhd:1273:25: can't associate 'arlen' with signal interface "axi_arlen_out" ../../HW/src/soc/soc_base.vhd:1273:25: (type of 'arlen' is an erroneous type) ../../HW/src/ztachip_pkg.vhd:1126:13: (type of signal interface "axi_arlen_out" is an erroneous type) ../../HW/src/top/ztachip.vhd:28:10: unit "numeric_std" not found in library "ieee" ../../HW/src/top/ztachip.vhd:38:49: no declaration for "unsigned" ../../HW/src/top/ztachip.vhd:54:49: no declaration for "unsigned" ../../HW/src/soc/tcm.vhd:28:10: unit "std_logic_textio" not found in library "ieee" ../../HW/src/soc/tcm.vhd:28:10: (use --ieee=synopsys or --std=08 for this non-standard synopsys package) ../../HW/src/soc/tcm.vhd:29:10: unit "numeric_std" not found in library "ieee" ../../HW/src/soc/peripherals/time.vhd:21:10: unit "numeric_std" not found in library "ieee" ../../HW/src/soc/peripherals/gpio.vhd:21:10: unit "numeric_std" not found in library "ieee" ../../HW/src/soc/peripherals/uart.vhd:21:10: unit "numeric_std" not found in library "ieee" ../../HW/src/soc/peripherals/vga.vhd:21:10: unit "numeric_std" not found in library "ieee" ../../HW/src/soc/peripherals/camera.vhd:21:10: unit "numeric_std" not found in library "ieee"
I'm not familiar with the tool GHDL. Does this mean that I missed some configuration when using ./convert.sh, or I should download some library for the script?
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Thanks for the reply. Just as you said, the GHDL version is the reason. I also checked the issue on the GHDL repo; issue explains why lower versions (<1.0) could cause the error. I upgraded my GHDL (0.37) to 4.0, and now the The next question is about the Verilog project. I now create the project with soc.v., the synthesis part is fine, but the implementation fails, saying |
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Did you build with Vivado?
Also try with GHDL that comes with ztachip repo (under ztachip/tools/ghdl/ghdl)
…________________________________
From: kevinli-hw ***@***.***>
Sent: April 6, 2025 11:14 AM
To: ztachip/ztachip ***@***.***>
Cc: ztachip ***@***.***>; Mention ***@***.***>
Subject: Re: [ztachip/ztachip] Verilog version (Issue #19)
Thanks for the reply. Just as you said, the GHDL version is the reason. I also checked the issue on the GHDL repo; issue<ghdl/ghdl#1686> explains why lower versions (<1.0) could cause the error. I upgraded my GHDL (0.37) to 4.0, and now the convert.sh works fine.
The next question is about the Verilog project. I now create the project with soc.v., the synthesis part is fine, but the implementation fails, saying [Route 35-2] Design is not legally routed. There are 81084 node overlaps. The VHDL project doesn't have the error, so I guess this is still because I miss some configurations. It would be great if you could give some suggestions.
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[kevinli-hw]kevinli-hw left a comment (ztachip/ztachip#19)<#19 (comment)>
Thanks for the reply. Just as you said, the GHDL version is the reason. I also checked the issue on the GHDL repo; issue<ghdl/ghdl#1686> explains why lower versions (<1.0) could cause the error. I upgraded my GHDL (0.37) to 4.0, and now the convert.sh works fine.
The next question is about the Verilog project. I now create the project with soc.v., the synthesis part is fine, but the implementation fails, saying [Route 35-2] Design is not legally routed. There are 81084 node overlaps. The VHDL project doesn't have the error, so I guess this is still because I miss some configurations. It would be great if you could give some suggestions.
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Sorry for the late reply.
Yes, I'm using Vivado 2024.2.
I tried the GHDL from the repo, which is 5.0.0. Following the manual, I used the tcl script to create the project with the generated soc.v. Though I didn't receive the previous message, the implementation still failed due to some critical warnings, something related to |
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Remove the lines below in HW/examples/GHRD/main.xdc. They are for signal tap debugging which you don't need.
set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
connect_debug_port dbg_hub/clk [get_nets clk]
…________________________________
From: kevinli-hw ***@***.***>
Sent: April 11, 2025 7:17 AM
To: ztachip/ztachip ***@***.***>
Cc: ztachip ***@***.***>; Mention ***@***.***>
Subject: Re: [ztachip/ztachip] Verilog version (Issue #19)
[https://avatars.githubusercontent.com/u/189257180?s=20&v=4]kevinli-hw left a comment (ztachip/ztachip#19)<#19 (comment)>
Sorry for the late reply.
Did you build with Vivado?
Yes, I'm using Vivado 2024.2.
Also try with GHDL that comes with ztachip repo (under ztachip/tools/ghdl/ghdl)
I tried the GHDL from the repo, which is 5.0.0. Following the manual, I used the tcl script to create the project with the generated soc.v. Though I didn't receive the previous message, the implementation still failed due to some critical warnings, something related to debug_hub in the constraints.
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Thanks for your patience. Now the implementation succeeds after removing these lines. The design failed to meet the timing requirements, but I see your demo runs correctly. Is it necessary to fix all the violations if I want to deploy my own model? |
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The timing violation is usually for worst case under highest temperature. If you are not at that operating range, the current timing violation is within tolerable range.
But if you want to remove all warning to work at any conditions, you may need to reduce the clock from 125M to 100M. Clock is defined in the script when you create the project.
…________________________________
From: kevinli-hw ***@***.***>
Sent: April 14, 2025 5:54 AM
To: ztachip/ztachip ***@***.***>
Cc: ztachip ***@***.***>; Mention ***@***.***>
Subject: Re: [ztachip/ztachip] Verilog version (Issue #19)
[https://avatars.githubusercontent.com/u/189257180?s=20&v=4]kevinli-hw left a comment (ztachip/ztachip#19)<#19 (comment)>
Thanks for your patience. Now the implementation succeeds after removing these lines. The design failed to meet the timing requirements, but I see your demo runs correctly. Is it necessary to fix all the violations if I want to deploy my own model?
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Got it. I'll try your method. Thanks again for your patience. |
where can I find the verilog versions of the ztachip as Iam not familiar with the VHDL
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