8000 Some questions about simulation · Issue #10 · ztachip/ztachip · GitHub
[go: up one dir, main page]
More Web Proxy on the site http://driver.im/
Skip to content

Some questions about simulation #10

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom
Open
fanjl123 opened this issue Feb 29, 2024 · 1 comment
Open

Some questions about simulation #10

fanjl123 opened this issue Feb 29, 2024 · 1 comment

Comments

@fanjl123
Copy link
fanjl123 commented Feb 29, 2024 •
edited
Loading

Hello! I am a graduate student and I would like to delve deeper into the design of your code in the main.m file. There are some parts of the logic that are not very clear to me, and I would like to ask you for some guidance on how to gain a deeper understanding of your design. Where should I start if I want to understand your design more thoroughly?

if(c_len` > 0) {
      > DTYPE(INT16) PCORE[*].root.constant[0:c_len-1] <= DTYPE(INT16)MEM((uint32_t)c_p)[0:c_len-1];
   }
   ZTAM_GREG(0,REG_DP_VM_TOGGLE,0)=0;

   // Set pcore process0's constant memory space.
   if(c_len > 0) {
      > DTYPE(INT16) PCORE[*].root.constant[0:c_len-1] <= DTYPE(INT16)MEM((uint32_t)c_p)[0:c_len-1];
   }
ZTAM_GREG
   // Set pcore code space
   > PROG((pcoreLen>>1)) <= DTYPE(INT16)MEM((uint32_t)pcore_p,(pcoreLen>>1)<<2)[:];
   > BARRIER;
@ztachip
Copy link
Owner
ztachip commented Mar 14, 2024 via email

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Assignees
No one assigned
Labels
None yet
Projects
None yet
Milestone
No milestone
Development

No branches or pull requests
2 participants
@ztachip @fanjl123
0