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Python 3.12 backport for Debian 12 bookworm

Dockerfile 21 Updated Feb 10, 2025

Add-on for Home Assistant to connect JK, JBD, Daly, ANT, SOK and Supervolt BMS via Bluetooth

Python 388 73 Updated Mar 28, 2025

Xilinx Platform Cable USB II (DLC9LP) driver

C 5 2 Updated Nov 18, 2023

Xilinx Virtual Cable Daemon

C 117 63 Updated Mar 6, 2025

Xilinx Virtual Cable Server for Raspberry Pi

C 114 28 Updated Mar 14, 2022

Multi-Technology RAM with AHB3Lite interface

SystemVerilog 23 15 Updated May 10, 2024

A test case for stress testing Tang Nano 4K and 9K and Primer 20K (Gowin FPGAs)

Verilog 43 3 Updated Dec 6, 2024

A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals

Verilog 238 32 Updated Nov 29, 2018

QBUS Storage and I/O Card

Verilog 11 1 Updated Jan 6, 2024

Raspberry Pico powered Xilinx Virtual Cable - Xilinx JTAG Cable!

C 9 1 Updated Jun 2, 2022

Verilog wishbone components

Python 115 33 Updated Jan 5, 2024

Quickly update a bitstream with new RAM contents

Verilog 15 3 Updated Jun 8, 2021

FPGA-версия платы МС1201.02 и ЭВМ ДВК-3

Verilog 11 6 Updated Mar 2, 2021

FPGA-версия терминалов VT52 и 15ИЭ-00-013

Verilog 13 5 Updated Nov 20, 2020

EDK II

C 30 7 Updated Sep 3, 2018

Порт конфигурации Reverse u16_speccy на плату ZrTech WXEDA

VHDL 9 2 Updated Dec 15, 2017

Ted Fried's MicroCore Labs Projects which include microsequencer-based FPGA cores and emulators for the 8088, 8086, 8051, 6502, 68000, Z80, Risc-V, and also Typewriter and EPROM Emulator projects. …

C++ 434 86 Updated Apr 16, 2025

Revengineered ancient PDP-11 CPUs, originals and clones

Verilog 159 27 Updated May 31, 2025

An attempt to provide tools and LDIF schemas for conversion of Active Directory structures to OpenLdap.

Python 122 36 Updated Jun 16, 2022

pathogen.vim: manage your runtimepath

Vim Script 12,142 1,159 Updated Aug 24, 2022

Allows to write net-snmp subagents in Python.

Python 70 38 Updated Oct 28, 2024
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