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Starred repositories

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VHDL 1 Updated Aug 9, 2021
Verilog 20 5 Updated May 18, 2022

32-bit Superscalar RISC-V CPU

Verilog 1,049 179 Updated Sep 18, 2021

GPGPU supporting RISCV-V, developed with verilog HDL

Verilog 102 20 Updated Feb 24, 2025

PainterEngine is a application/game engine with software renderer,PainterEngine can be transplanted to any platform that supports C

C 2,931 319 Updated Jun 24, 2025

Hardware Description Language Translator

SystemVerilog 17 5 Updated May 28, 2025

The OpenPiton Platform

Assembly 714 240 Updated May 20, 2025

a multi-cpu with gpgpu project running on the xilinx zynq board(zc706)

VHDL 7 1 Updated Jan 26, 2018
Verilog 8 1 Updated Aug 11, 2015

GPGPU microprocessor architecture

C 11 5 Updated Jan 22, 2020

OpenSource GPU, in Verilog, loosely based on RISC-V ISA

SystemVerilog 1,029 118 Updated Nov 22, 2024

A collection of license features from a varity of EDA vendors

Python 69 27 Updated Aug 17, 2023

Various caches written in Verilog-HDL

Verilog 125 41 Updated Apr 24, 2015

GPGPU microprocessor architecture

C 2,095 361 Updated Nov 8, 2024

General Purpose Graphics Processing Unit (GPGPU) Core

C 2 Updated Jan 30, 2015
SystemVerilog 5 5 Updated Jul 3, 2025

the uvm environment generating with python

Python 2 Updated Nov 14, 2023

L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC

Verilog 13 5 Updated Aug 18, 2022

one colorscheme pack to rule them all!

Vim Script 3,452 631 Updated Sep 9, 2021

acp was a fork of the vim plugin autocomplpop (2.14.1) - I've switched to a new neovim setup and no longer maintain this

Vim Script 11 6 Updated Feb 5, 2013

Help folks to align text, eqns, declarations, tables, etc

Vim Script 135 30 Updated Apr 1, 2013

Verilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.

SystemVerilog 272 95 Updated Jan 26, 2025

Automatically exported from code.google.com/p/mcclanahoochie

Emacs Lisp 5 1 Updated Aug 25, 2015

A code-completion engine for Vim

Python 25,800 2,791 Updated Jun 27, 2025

SystemVerilog vim scripts

Vim Script 68 22 Updated Jan 25, 2023

Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators

Verilog 667 110 Updated Jun 24, 2025

Basic RISC-V CPU implementation in VHDL.

VHDL 167 17 Updated Sep 13, 2020

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

VHDL 1,796 270 Updated Jun 27, 2025
Verilog 1,564 336 Updated Jul 3, 2025

A darkblue color scheme.

Vim Script 3 Updated Apr 8, 2012
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