Stars
C++ library for Infineon's motor system ICs TLE956x family
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
AXI Adapter(s) for RISC-V Atomic Operations
Verilog Ethernet components for FPGA implementation
IBM PC Compatible SoC for a commercially available FPGA board
Mnist with CMSIS NN and deploy on RT-Thread, without STM32Cube AI
A higher-level Neural Network library for microcontrollers.
RTL Verilog library for various DSP modules
tcl scripts used to build or generate vivado projects automatically
TCL framework to package Vivado IP-Cores
频率和周期的转换计算小工具🛠。 A conversion and calculation tool for frequency and period🛠.
Infrastructure to enable deployment of ML models to low-power resource-constrained embedded targets (including microcontrollers and digital signal processors).
Implementation of a Tensor Processing Unit for embedded systems and the IoT.
Digital Logic Lecture Final Project in the first term of year 2020-21
Examples for iCE40 UltraPlus FPGA: BRAM, SPRAM, SPI, flash, DSP and a working RISC-V implementation
80186 compatible SystemVerilog CPU core and FPGA reference design
Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
xfguo / riscv-openwrt
Forked from openwrt/openwrtPorting OpenWrt to RISC-V - please check https://github.com/xfguo/riscv-openwrt-port for full instructions.
Openwrt favorite linux kernel version. (4.1.16)