- model : jeremywu3 50%
- cnn acc: JiaMingLin 50%
- soc: wubinary 0.01%
cowork power-chips
- Platform: Zynq UltraScale+ MPSoC ZCU102
- Enviroment: Vivado 2019.1
- Vivado HLS implementations
- System flow:
#### run hls cnn + bitstream
> make
#### run bitstream only
> make bitstream
#### run hls cnn
> make hls