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Parallel Programming for FPGAs -- An open-source high-level synthesis book
BYU Pynq PR Video Pipeline Hardware
Generates a SystemVerilog assertion interface for a given SV RTL design
Full-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our d…
The Demo that was presented at FCCM.
BYU Pynq PR Video Pipeline Hardware
Xst Reader is an open source viewer for Microsoft Outlook’s .ost and .pst files, written entirely in C#. To download an executable of the current version, go to the releases tab.
The tutorial includes practical examples of memory initialization using coefficient (.coe) files
Learn how to design and implement a Numerically Controlled Oscillator (NCO) in Vivado using a block design approach!
CORDIC IP Tutorial: Creating NCO for Sine and Cosine Generation in Vivado
build a complete analog signal processing system with XADC using PYNQ Z2 FPGA board.
freeCodeCamp.org's open-source codebase and curriculum. Learn math, programming, and computer science for free.
A huge collection of VHDL/Verilog open-source IP cores scraped from the web
vengin / FileIcons
Forked from braver/FileIconsFile icons for Sublime Text
SublimeLinter plugin for using ModelSim/QuestaSim vcom to lint VHDL
vengin / SublimeCalculate
Forked from colinta/SublimeCalculateSelect a formula and evaluate it using python.
vengin / hart-protocol
Forked from yaq-project/hart-protocolA sans-io python implementation of the Highway Addressable Remote Transducer Protocol