Hua-Chen Wu
trista.cs11@nycu.edu.tw; huachen.cs11@gmail.com | LinkedIn | GitHub |
Dynamic Design Verification Engineer adept in FPGA hardware-software co-design, UVM methodologies, SystemVerilog, and advanced data privacy technologies. Demonstrates an innovative and analytical mindset, capable of addressing complex verification challenges and implementing cutting-edge solutions. Committed to continuous learning, proactive collaboration, and delivering significant organizational impact.
National Yang Ming Chiao Tung University
College of Computer Science (Sep 2022 – Jun 2025)
- SilverCareHousing – Privacy-Enhanced Elderly Housing and Care Needs Analysis:
- Implemented advanced privacy algorithms (k-anonymity, l-diversity, differential privacy), dynamically balancing data privacy and usability.
- Developed hybrid synthetic data generation (VAE and GAN) with rigorous privacy and utility assessment metrics.
- Utilized advanced visualization (t-SNE, UMAP, heatmaps, pairplots) to explore complex multi-factor interactions clearly and intuitively.
- Awarded 2nd place in the International ICT Innovative Services Awards 2024, reflecting innovation and significant practical impact.
- SiCADA Advanced Design and Verification Training:
- Completed 100+ hours of specialized training in Digital Design, Advanced Function Verification, and SoC Frontend Design, mastering essential industry verification skills.
- AMBA5 AHB-Lite Design & Verification Project:
- Led the successful integration and synchronization of AHB, APB, and DMA interfaces within a unified RTL design, addressing intricate timing and synchronization challenges.
- Developed a comprehensive UVM verification environment featuring specialized protocol agents and dual-layer (scoreboard-level and interface-level) coverage strategies, ensuring accurate and thorough verification from transactions to protocol compliance.
- Implemented robust, dual-layer coverage methods systematically validating transaction-level accuracy and signal-level timing precision.
- FPGA-Accelerated LLM Inference Optimization:
- Independently designed and implemented a hardware-software co-design framework for FPGA-accelerated inference, significantly enhancing performance and efficiency.
- Hardware & Verification: SystemVerilog, Verilog, FPGA Design (Xilinx Alveo U200)
- Programming Languages: C/C++, Python, C#, Swift
- Verification Frameworks: UVM, AHB-Lite, AMBA protocols
- Data Privacy & Analytics: Differential Privacy, VAE, GAN, t-SNE, UMAP
- System Integration: FPGA-AI inference optimization, hardware-software co-design
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SiCADA Purple 100+ (SiCADA 500) (2024)
- Specialized practical training in digital IC verification methodologies.
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SiCADA600 AMBA5 AHB-Lite Verification Project (2024)
- Comprehensive experience with full verification cycles using industry-standard UVM environments.
- Proven track record of mastering advanced verification and FPGA optimization techniques rapidly and effectively.
- Passionate and proactive collaborator, consistently fostering team synergy and sharing critical knowledge.
- Highly analytical problem-solver, adept in identifying and resolving sophisticated verification and design challenges.
Aspire to excel as a leading Design Verification Engineer, driving technological innovation, robust verification strategies, and delivering tangible value to advance organizational objectives.