Seven Segment Interface with Tang Primer
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Updated
Jan 4, 2021 - Verilog
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sipeed
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First steps with the Sipeed Tang Primer 20k FPGA.
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Updated
May 5, 2025 - Verilog
This project implements a BCD (Binary-Coded Decimal) converter that reads DIP switch input and controls a 7-segment display, showing digits 0–8 or ‘E’ for invalid combinations.
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Updated
May 5, 2025 - Verilog
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