Approximate layers - TensorFlow extension
Approximate Multipliers of 8bit and 16bit operands, built with approximate compressors.
Parameterized and 4-bit carry save multiplier design
Verilog Codes for various digital circuits for labs at IIT Ropar, basic gates, adders & subtractors (half & full), ripple adders, multipliers and code converters.
Design and Analysis of an FPGA-based Wallace Multiplier.
A 32-bit Signed Vedic Multiplier created using Verilog HDL utilising Vedic Mathematic Sutras formed using Carry Lookahead Adders as the basic building blocks.
idle game thingy.
Different Multipliers code in VHDL and Comparison
Useful VHDL scripts for hardware description.
Digital design project for a simple integer multiplier using Booth's multiplication algorithm made through ASM design method
The computational speed of the dadda multiplier can be enhanced by partitioning the partial products. In process to achieve low power we have considered pass transistor for logical implementation.
Verilog Multiplier Implementation
Character typing game using TypeScript
Bingo game with score
Compiled set of verilog codes for beginners. Can help you with getting started with basics of verilog.
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