Python tools for generating and testing SPICE netlists/waveforms involving crossbar memory arrays in various configurations

Design of 6T, 8T and 10T SRAM Cells with Static Noise Margin Analysis

This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.

Behavioral architecture of a read/write cycle controller for a DRAM chip.