Digital clock implemented in vhdl for the Basys 3 Board from Digilent.
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Dec 14, 2020 - VHDL
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Digital clock implemented in vhdl for the Basys 3 Board from Digilent.
A music box and 13-note organ for Nexys 3 Spartan 6 FPGA Board. The final project of Digital System Design (EE 240) at Boğaziçi University, June 2017
The source code for a car parking system which automates the boom barrier of the homeowners' parking garage and includes fire detection support. Code is written in VHDL and implemented on Altera DE10-Lite FPGA
Customizable MIDI buzzer system built with VHDL for hardware logic and assembly for configuration. Supports full control over sound parameters like frequency (20 Hz – 20 kHz), volume, and duration.
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