write-around

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Rex1110 / Cache

A direct-mapped L1 cache supporting byte-, halfword-, and word-level accesses. Implements read-allocate on read miss and write-around on write miss, with proper hit/miss handling. Both design and verification focus on correctness across various access patterns.

cache assertions systemverilog testbench hardware-design l1-cache write-around

Updated Mar 29, 2025
SystemVerilog

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write-around

Here is 1 public repository matching this topic...

Rex1110 / Cache

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