vivado-simulator

Here are 16 public repositories matching this topic...

suoto / hdl_checker

Repurposing existing HDL tools to help writing better code

Updated Jun 6, 2024
Python

Arjun-Narula / Traffic-Light-Controller-using-Verilog

the project includes system design of a t intersection traffic light controller and its verilog code in vivado design suite.

traffic verilog vivado verilog-hdl traffic-light traffic-sign-recognition vivado-hls verilog-programs verilog-simulator verilog-project verilog-code vivado-simulator

Updated Jul 18, 2020
JavaScript

wyvernSemi / mem_model

Star

High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model

simulation vhdl verilog questasim ghdl avalon memory-model test-bench pli verilog-components verilator axi nvc dpi-c cosimulation vivado-simulator verilog-testbenches

Updated Nov 20, 2024
VHDL

esynr3z / pyhdlsim

Star

Example of Python and PyTest powered workflow for a HDL simulation

python asic fpga pytest rtl verilog icarus-verilog hdl modelsim system-verilog vivado-simulator

Updated Jan 17, 2021
Python

mzh330521 / SublimeLinter-contrib-xsim

Star

Vivado Simulator (XSim) xvlog/xvhdl plugin for SublimeLinter. Linting for Verilog/SystemVerilog and VHDL.

sublime-text vhdl sublimelinter linter-plugin verilog systemverilog xsim vivado-simulator

Updated May 29, 2024
Python

arhamhashmi01 / Axi4-lite

Star

This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.

systemverilog hardware-designs verilator axi4-lite axi4-protocol vivado-simulator axi4-lite-interface

Updated May 4, 2024
SystemVerilog

RipperJ / VerilogExpr2NAND-NOR

Star

Logic Expression Compiler, with Logic Minimization, to NAND/NOR Implementation

compiler simulation lex espresso ply verilog yacc boolean-expression nand logic-minimization nor xsim vivado-simulator pyeda

Updated Jun 4, 2023
Python

Ammar-Bin-Amir / SystemVerilog_Practice

Star

Practice Codes of SystemVerilog Language

vscode systemverilog vivado-simulator

Updated May 19, 2024
SystemVerilog

amirah-sri / all_verilog

Star

I am trying to develop my skills through daily practice and consistency.

verilog vivado vlsi verilog-hdl verilog-programs verilog-project verilog-code vivado-simulator

Updated Jul 31, 2024
Verilog

TahirZia-1 / UART-Transmitter-and-Receiver

Star

A complete UART (Universal Asynchronous Receiver/Transmitter) implementation for FPGAs, written in Verilog HDL. This project includes transmitter and receiver modules, baud rate generation, and test infrastructure for both simulation and hardware validation.

simulation rtl verilog vivado uart systemverilog uart-verilog fpga-soc testbench verilog-hdl fpga-board vivado-hls nexys4ddr verilog-project uart-transmitter uart-receiver fpga-programming vivado-simulator

Updated Feb 28, 2025
SystemVerilog

bp0609 / Mini-Processor-Verilog-FPGA-Implemented

Star

This repo contains a mini-processor design implemented on FPGA using verilog

verilog fpga-board vivado-simulator

Updated May 27, 2024
Verilog

anr2311 / I2C_State_Machine

Star

This repo contains an I2C transaction state machine modelled in Verilog targeted for the Zynq Zedboard

i2c-bus vivado-simulator

Updated Nov 23, 2024
Verilog

Imtjl / digital-design-fundamentals

Star

Digital design fundamentals - a 3rd year CSE banchelor course in ITMO University

circuits system-verilog verilog-hdl digital-design spice-simulator vivado-simulator system-verification

Updated Nov 25, 2024
Tcl

WimukthiMadushan / Computer-Organization-and-Digital-Design

Star

Includes lab exercises from my Computer Organization and Digital Design module. It features implementations of various components inside a processor using VHDL . Finally I make 4 bit nanoprocessor combining all components those build in previous labs.

vhdl vivado vhdl-code vivado-simulator nanoprocessor

Updated Jan 25, 2024
VHDL

rishz09 / digital-safe-verilog

Star

A digital safe designed in Vivado, which has a 4 digit decimal password, and is implemented on PYNQ-Z2 board and RPI-Logic board

verilog vivado digital-design verilog-project pynq-z2 vivado-simulator digital-safe

Updated Jul 1, 2024
Tcl

TahirZia-1 / Digital-Clock-Verilog

Star

This repository contains a Verilog implementation of a 24-hour digital clock designed for FPGA platforms. The design displays hours, minutes, and seconds on a 7-segment display, providing a complete timekeeping solution that can be easily integrated into various FPGA development boards.

fpga simulation verilog synthesis vivado systemverilog fpga-soc verilog-hdl 7segment systemverilog-hdl digitalclock nexys4ddr fpga-programming vivado-simulator

Updated Feb 28, 2025
Tcl

Improve this page

Add a description, image, and links to the vivado-simulator topic page so that developers can more easily learn about it.

Curate this topic

Add this topic to your repo

To associate your repository with the vivado-simulator topic, visit your repo's landing page and select "manage topics."

Learn more

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

vivado-simulator

Here are 16 public repositories matching this topic...

suoto / hdl_checker

Arjun-Narula / Traffic-Light-Controller-using-Verilog

wyvernSemi / mem_model

esynr3z / pyhdlsim

mzh330521 / SublimeLinter-contrib-xsim

arhamhashmi01 / Axi4-lite

RipperJ / VerilogExpr2NAND-NOR

Ammar-Bin-Amir / SystemVerilog_Practice

amirah-sri / all_verilog

TahirZia-1 / UART-Transmitter-and-Receiver

bp0609 / Mini-Processor-Verilog-FPGA-Implemented

anr2311 / I2C_State_Machine

Imtjl / digital-design-fundamentals

WimukthiMadushan / Computer-Organization-and-Digital-Design

rishz09 / digital-safe-verilog

TahirZia-1 / Digital-Clock-Verilog

Improve this page

Add this topic to your repo