A simple computer architecture, ISA and Interpreter build with Rust.
The name comes from the Von Neumann Model.
The basic idea behind this design is to follow some tips from the book Structured Computer Organization - Andrew S. Tanenbaum while implementing the ability to perform operations even if the main clock is in a non-edge level in order to reduce clock cycles.
For that we will use two datapaths with one ALU each, but the clock trigger of one is the opposite of the other, that is, ALU1 is falling-edge triggered and ALU2 is rising-edge triggered. Furthermore, the clock signal received in ALU2 is a function of the clock signal of ALU1.
Let's say that ALU1 has a clock α1 and the delayed version of this signal is α1'. So the ALU2 must have a clock α2 = (α1 ∧ α1') plus a delay of δ1 as shown below:
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| The relation between the clock α1 and α2. |
In other words, ALU1 will start its operation cycle on the falling-edge of α1 and end the operation on the rising-edge, while ALU2 will start its operation cycle on the rising-edge of α2 and end the operation on the falling-edge, taking advantage of the main clock (α1) even when it is at high level.
The advantage of this method is that we can share the control store and all the registers without big cost in the Misconstruction size, external hardware components and additional logic steps that may cost some clock cycles. The way that the components are shared is shown below:
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| The datapaths share some components such as the Microprogram, RAM and shared registers. |
The way that each datapath is structured is not far from the usual three-bus design plus a IFU, the techniques involved a rather simple for now as you can see the diagram below:
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| The diagram of a single datapath (click to zoom). |
Those two datapaths will become a thread
in a future design of this Microarchitecture that is planned to have two task parallel threads.
The implementation of this design is provided by the uarch module.