ATPGnFaultSim

An automatic test pattern generator and deductive fault simulator for digital logic circuits

Name		Name	Last commit message	Last commit date
Latest commit History 2 Commits
.vscode		.vscode
.gitignore		.gitignore
ECE6140_Project_Part2.cpp		ECE6140_Project_Part2.cpp
ECE6140_Project_Part3.cpp		ECE6140_Project_Part3.cpp
README.md		README.md
d_s27.txt		d_s27.txt
d_s344f_2.txt		d_s344f_2.txt
d_s344ff_2.txt		d_s344ff_2.txt
d_test.txt		d_test.txt
f_s27.txt		f_s27.txt
f_s298f_2.txt		f_s298f_2.txt
f_s344f_2.txt		f_s344f_2.txt
f_s344ff_2.txt		f_s344ff_2.txt
f_s349f_2.txt		f_s349f_2.txt
f_test.txt		f_test.txt
i_s27.txt		i_s27.txt
i_s344f_2.txt		i_s344f_2.txt
i_s344ff_2.txt		i_s344ff_2.txt
i_s349f_2.txt		i_s349f_2.txt
i_test.txt		i_test.txt
o_s27.txt		o_s27.txt
o_s298f_2.txt		o_s298f_2.txt
o_s344f_2.txt		o_s344f_2.txt
o_s344ff_2.txt		o_s344ff_2.txt
o_s349f_2.txt		o_s349f_2.txt
o_test.txt		o_test.txt
output.txt		output.txt
s27.txt		s27.txt
s298f_2.txt		s298f_2.txt
s344f_2.txt		s344f_2.txt
s344ff_2.txt		s344ff_2.txt
s349f_2.txt		s349f_2.txt
test.txt		test.txt

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