8000 six658 / Starred · GitHub
[go: up one dir, main page]
More Web Proxy on the site http://driver.im/
Skip to content
View six658's full-sized avatar

Block or report six658

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Showing results

A Chi­nese edi­tion of the Not So Short Introduction to LaTeX2ε

TeX 3,318 434 Updated Dec 19, 2024

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

Python 3,191 417 Updated Oct 28, 2024

Official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022)

Python 76 21 Updated Aug 22, 2024

OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/

Verilog 452 365 Updated Jul 5, 2025

ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino

VHDL 55 17 Updated May 14, 2025

Material for OpenROAD Tutorial at DAC 2020

Python 47 18 Updated Dec 8, 2022

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

Verilog 2,031 687 Updated Jul 5, 2025

A General-purpose Task-parallel Programming System using Modern C++

C++ 11,016 1,290 Updated Jun 30, 2025

Spice# is a cross-platform electronic circuit simulator based on Berkeley Spice - the mother of commercial industry-standard circuit simulators.

C# 270 51 Updated Dec 4, 2024

Simulate electronic circuit using Python and the Ngspice / Xyce simulators

Python 732 187 Updated Aug 13, 2024

Icarus Verilog

C++ 3,086 558 Updated Jul 5, 2025

Algorithms for incremental timing analysis

C++ 4 1 Updated Jan 29, 2017

Second Prize solution to the 2016 ICCAD Contest Problem D

C++ 6 1 Updated Oct 8, 2023

A static timing analysis tool that gets (1) the Verilog gate level net list of a digital circuit, (2) the library of the cells used in the circuit, (3) the net capacitances file, (4) the clocks ske…

Python 7 1 Updated May 24, 2017

🕒 Static Timing Analysis diagram renderer

JavaScript 13 2 Updated Dec 13, 2023

Documentation on how to perform static timing, with detailed examples on writing constraints and how to validate timing reports.

4 4 Updated Jan 24, 2022

Tatum: A Fast, Flexible Static Timing Analysis (STA) Engine for Digital Circuits

C++ 62 11 Updated May 28, 2024
0