GitHub - shirishbahirat/cpu: risc-v single cycle implementation

Name		Name	Last commit message	Last commit date
Latest commit History 28 Commits
alu.v		alu.v
alu_control.v		alu_control.v
alu_mux.v		alu_mux.v
control.v		control.v
cpu.py		cpu.py
cpu1.py		cpu1.py
cpu2.py		cpu2.py
cpu3.py		cpu3.py
cpu4.py		cpu4.py
decode.v		decode.v
decode.xlsx		decode.xlsx
decoder.py		decoder.py
defs.py		defs.py
idex_pipl.v		idex_pipl.v
ifid_pipl.v		ifid_pipl.v
imm_gen.v		imm_gen.v
inst_mem.v		inst_mem.v
jmp_adder.v		jmp_adder.v
mc_code		mc_code
mc_data		mc_data
pc_adder.v		pc_adder.v
pc_assign.v		pc_assign.v
pc_mux.v		pc_mux.v
pipelined.py		pipelined.py
reg_file.v		reg_file.v
riscv-cpu.py		riscv-cpu.py
taken.v		taken.v
tb_alu.v		tb_alu.v
tb_alu_control.v		tb_alu_control.v
tb_alu_mux.v		tb_alu_mux.v
tb_control.v		tb_control.v
tb_decode.v		tb_decode.v
tb_idex_pipl.v		tb_idex_pipl.v
tb_ifid_pipl.v		tb_ifid_pipl.v
tb_imm_gen.v		tb_imm_gen.v
tb_inst_mem.v		tb_inst_mem.v
tb_jmp_adder.v		tb_jmp_adder.v
tb_pc_adder.v		tb_pc_adder.v
tb_pc_assign.v		tb_pc_assign.v
tb_pc_mux.v		tb_pc_mux.v
tb_reg_file.v		tb_reg_file.v
tb_taken.v		tb_taken.v
tb_wda_mux.v		tb_wda_mux.v
top.vcd		top.vcd
wda_mux.v		wda_mux.v