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J1 Forth cross compiler

Forth 4 1 Updated Apr 18, 2021

Forth CPU J1 in Bluespec SystemVerilog (BSV)

Verilog 7 1 Updated Apr 30, 2023

Forth CPU J1 in SystemVerilog and Wishbone interface

SystemVerilog 7 2 Updated Oct 3, 2018

Forth CPU J1 in SystemVerilog

Forth 15 5 Updated Apr 29, 2017

MicroPython - a lean and efficient Python implementation for microcontrollers and constrained systems

C 1 Updated < 3254 relative-time datetime="2023-11-05T22:28:17Z" class="no-wrap">Nov 5, 2023

Board repo for the ZCU216 RFSOC

Shell 29 18 Updated Jun 9, 2022
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