This repository contains a chisel version of the laboratory of the Zhejiang University Logic and Computer Design Fundamentals course.
Notice: The board used here is Nexys A7, not the SWORD board used in the class.
Currently, we support compile (chisel -> verilog) and sythesis (verilog -> bit) process. To compile the code, you need install sbt from here.
You can select your target lab and task by using LAB and CONFIG variables.
# After install sbt
make LAB=4 CONFIG=LampCtrlTargetLabs List:
- Lab4: LampCtrlTarget, LampCtrlDelayTarget
- Lab5: DecodeTestTarget, LampCtrlTarget
- Lab6: DecodeTestTarget
- Lab7: TopTarget
- Lab8: TopTarget
- Lab11: cnt4bTarget, cnt16bTarget
- Lab12: Task1Target, Task2Target, Task3Target
- Lab13: LEDTarget, SEGTarget
- Lab14: ClockTarget
Using chisel-test is not a good choice, I recommend you use iverilog, verilator, vivado and other EDA (e.g. synopsys vcs, mentor modelsim) to simulate your design.
Use synthesis target to generate the bitstream.
make synthesis LAB=4 CONFIG=LampCtrlTargetUse fpga target to program your board.
make fpga LAB=4 CONFIG=LampCtrlTargetIn vivado IDE, select Flow - Open Hardware Manager to load bit file under build/vivado/digit/lab? into your board.