Stars
AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made in the signal declaration section of an RTL module, generat…
Verilog evaluation benchmark for large language model
A curated list of repositories in which many NLP/CV/ML papers and related area resources are collected.
This repo includes ChatGPT prompt curation to use ChatGPT and other LLM tools better.
HDLBits website practices & solutions
🤗 Transformers: State-of-the-art Machine Learning for Pytorch, TensorFlow, and JAX.
Collection of digital hardware modules & projects (benchmarks)
BaseJump STL: A Standard Template Library for SystemVerilog
ITC'99 benchmarks developed in the CAD Group at Politecnico di Torino
A collection of ISCAS,ITC,TAU and other Benchmark Circuits for EDA tool evaluation.
Code and model for the paper "Improving Language Understanding by Generative Pre-Training"
A minimalistic and high-performance SAT solver
NeuroCore: Guiding CDCL with Unsat-Core Predictions
An Extensible Toolkit for Finetuning and Inference of Large Foundation Models. Large Models for All.
A Modeling and Verification Platform for SoCs using ILAs
RISC-V Formal Verification Framework
REST, a reinforcement learning framework for constructing rectilinear Steiner Minimum tree (RSMT)
Flute3 is an open-source rectilinear Steiner minimum tree heuristic from Iowa State, with UFRGS improvements
Pono: A flexible and extensible SMT-based model checker
A generic C++ API for SMT solving. It provides abstract classes which can be implemented by different SMT solvers.
Reads a state transition system and performs property checking
A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core
Bo-Yuan-Huang / ILAng
Forked from PrincetonUniversity/ILAngA Modeling and Verification Platform for SoCs using ILAs
Here are my solutions to HDLbits Verilog problem sets (HDLbits: https://hdlbits.01xz.net/wiki/Main_Page).
A RISC-V CPU implementation
Python-based Hardware Design Processing Toolkit for Verilog HDL
Recent papers related to hardware formal verification.