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opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
A toy RV32I CPU that supports all RV32I unprivileged instructions except FENCE instructions.
A single cycle RISC-V CPU based on RV32I Instruction Set
Single Cycle CPU using the RV32I Base Instruction set
An FPGA Implementation of Arbiter PUF with 4x4 Switch Blocks
Robomaster超级电容充放电管理方案,该项目用作于Robomaster电容管理,使用单板在7.62cm* 7.62cm*2.5cm(高度主要是有个EC11旋钮有点小高)的超小体积下实现了集成度较高的双向buckboost控制,系统的响应频率高达200kHz。
The super capacitor project of RM2023 Enterprize team
A PyTorch implementation of the Deep SVDD anomaly detection method
Deep learning based one class classification code targeting one class image classification. Tests carried out on Abnormal image detection, Novel image detection and Active Authentication reported s…
利用pytorch实现图像分类的一个完整的代码,训练,预测,TTA,模型融合,模型部署,cnn提取特征,svm或者随机森林等进行分类,模型蒸馏,一个完整的代码
A pytorch implementation of Deep Graph Laplacian Regularization for image denoising
Noise2Noise: Learning Image Restoration without Clean Data - Official TensorFlow implementation of the ICML 2018 paper
LG-BPN: Local and Global Blind-Patch Network for Self-Supervised Real-World Denoising (CVPR 2023)
🦋A PyTorch implementation of BigGAN with pretrained weights and conversion scripts.
Code for the paper: CNN-generated images are surprisingly easy to spot... for now https://peterwang512.github.io/CNNDetection/