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  1. common_verification common_verification Public

    Forked from pulp-platform/common_verification

    SystemVerilog modules and classes commonly used for verification

    SystemVerilog

  2. tech_cells_generic tech_cells_generic Public

    Forked from pulp-platform/tech_cells_generic

    Technology dependent cells instantiated in the design for generic process (simulation, FPGA)

    SystemVerilog

  3. common_cells common_cells Public

    Forked from pulp-platform/common_cells

    Common SystemVerilog components

    SystemVerilog

  4. register_interface register_interface Public

    Forked from pulp-platform/register_interface

    Generic Register Interface (contains various adapters)

    SystemVerilog

  5. axi axi Public

    Forked from pulp-platform/axi

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

    SystemVerilog 1

  6. cvfpu cvfpu Public

    Forked from openhwgroup/cvfpu

    Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

    SystemVerilog

Repositories

Showing 10 of 26 repositories
  • FlooNoC Public Forked from pulp-platform/FlooNoC

    A Fast, Low-Overhead On-chip Network

    persimmonsai/FlooNoC’s past year of commit activity
    SystemVerilog 0 Apache-2.0 37 0 0 Updated May 5, 2025
  • snitch_cluster Public Forked from pulp-platform/snitch_cluster

    An energy-efficient RISC-V floating-point compute cluster.

    persimmonsai/snitch_cluster’s past year of commit activity
    C 0 Apache-2.0 64 0 0 Updated Apr 29, 2025
  • cvfpu Public Forked from openhwgroup/cvfpu

    Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

    persimmonsai/cvfpu’s past year of commit activity
    SystemVerilog 0 130 0 1 Updated Apr 22, 2025
  • iDMA Public Forked from pulp-platform/iDMA

    A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)

    persimmonsai/iDMA’s past year of commit activity
    SystemVerilog 0 30 0 0 Updated Apr 16, 2025
  • common_cells Public Forked from pulp-platform/common_cells

    Common SystemVerilog components

    persimmonsai/common_cells’s past year of commit activity
    SystemVerilog 0 164 0 0 Updated Apr 1, 2025
  • bender Public Forked from pulp-platform/bender

    A dependency management tool for hardware projects.

    persimmonsai/bender’s past year of commit activity
    Rust 0 Apache-2.0 47 0 0 Updated Mar 31, 2025
  • hero Public Forked from pulp-platform/hero

    Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.

    persimmonsai/hero’s past year of commit activity
    SystemVerilog 0 25 0 0 Updated Mar 27, 2025
  • hbm-utils Public

    HBM package and symbol generation scripts

    persimmonsai/hbm-utils’s past year of commit activity
    Python 0 0 0 0 Updated Mar 11, 2025
  • axi Public Forked from pulp-platform/axi

    AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

    persimmonsai/axi’s past year of commit activity
    SystemVerilog 0 291 0 0 Updated Feb 17, 2025
  • FABulous Public Forked from FPGA-Research/FABulous

    Fabric generator and CAD tools

    persimmonsai/FABulous’s past year of commit activity
    Python 0 Apache-2.0 38 0 0 Updated Oct 5, 2024

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