This module implements the basic interface you would expect from a standard TI 16550 UART. It exists because of current incompatibility of Verilator to understand our VHDL based UART. This UART will likely vanish with the release of our uDMA based peripherals.
This repository was archived by the owner on Sep 28, 2019. It is now read-only.
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pulp-platform/apb_uart_sv
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