8000 luojw-dwr (Jianwen Luo) / Starred · GitHub
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  • ShanghaiTech University
  • Pudong, Shanghai

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IDEA project source files

Verilog 106 42 Updated Nov 8, 2024

Prefix tree adder space exploration library

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Open-source high-performance RISC-V processor

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An MLIR-based toolchain for AMD AI Engine-enabled devices.

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Theano was a Python library that allows you to define, optimize, and evaluate mathematical expressions involving multi-dimensional arrays efficiently. It is being continued as PyTensor: www.github.…

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ABC: System for Sequential Logic Synthesis and Formal Verification

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Pixel Art Editor

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ROS overlay for the Nix package manager

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Fast, Accurate and Convenient Light-Weight HLS Framework for Academic Design Space Exploration and Evaluation. (LLVM-11)

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DASS HLS Compiler

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[FPGA 2021, Best Paper Award] An automated floorplanning and pipelining tool for Vivado HLS.

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HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing

Python 338 93 Updated Apr 20, 2024

A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.

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scratchip is a framework that can help to build your Chisel and Verilog/Systemverilog project easier.

Python 15 1 Updated Nov 2, 2022

A template project for beginning new Chisel work

Shell 637 190 Updated May 6, 2025
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