Stars
VHDL / PoC
Forked from VLSI-EDA/PoCIP Core Library - Published and maintained by the Open Source VHDL Group
HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-slang.
iic-jku / IIC-OSIC-TOOLS
Forked from efabless/foss-asic-toolsIIC-OSIC-TOOLS is an all-in-one Docker image for SKY130/GF180/IHP130-based analog and digital chip design. AMD64 and ARM64 are natively supported.
Network Development Kit (NDK) for FPGA cards with example application
An open source USB bootloader for FPGAs
USB Serial on the TinyFPGA BX
A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
VHDL/Verilog/SystemC code generator, simulator API written in python/c++
Generate Pinout Datasheet in SVG format, from a CSV source file of pin defintions
Amaranth HDL framework for monitoring, hacking, and developing USB devices
Vivado and PetaLinux projects for Zynq EBAZ4205 Board
A huge VHDL library for FPGA and digital ASIC development
A translation of the Xilinx XPM library to VHDL for simulation purposes
Tests to evaluate the support of VHDL 2008 and VHDL 2019 features
bkerler / Sniffle
Forked from nccgroup/SniffleA sniffer for Bluetooth 5 and 4.x LE
A Python package for generating HDL wrappers and top modules for HDL sources
High Speed Data Acquisition over HDMI - FPGA implementation
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
A dependency management tool for hardware projects.
FPGA verilog and firmware for TKey, the flexible and open USB security key 🔑