Starred repositories
Simple cache design implementation in verilog
In this repository, the hardware tests for the RTL code that you can find in my profile ("AXI2APB-Bridge-Design-and-Verification") will be tested using the JTAG to AXI Master IP Core provided by XI…
A project implementing Flappy Bird using Verilog
AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
Must-have verilog systemverilog modules
asynchronous fifo based on verilog
A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
AHB to AXI4 bridge design and verification.
Git Source Code Mirror - This is a publish-only repository but pull requests can be turned into patches to the mailing list via GitGitGadget (https://gitgitgadget.github.io/). Please follow Documen…
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超级速查表 - 编程语言、框架和开发工具的速查表，单个文件包含一切你需要知道的东西 ⚡
HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
Mill template for beginning your SpinalHDL project
automatic-verilog based on vimscript
An FPGA-based SD-card reader via SPI bus, which can read files from FAT16 or FAT32 formatted SD-cards. 基于FPGA的SD卡读取器(通过SPI总线)，可以从FAT16或FAT32格式的SD卡中读取文件。
TinyMaix is a tiny inference library for microcontrollers (TinyML).
An FPGA-based lightweight CAN bus controller. 基于FPGA的轻量级CAN总线控制器。
An FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。
2D Graphic Library optimized for Cortex-M processors
Verilog AXI components for FPGA implementation
SDK for Greenwaves Technologies' GAP8 IoT Application Processor