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SystemVerilog Functional Coverage for RISC-V ISA
OpenTitan: Open source silicon root of trust
Random instruction generator for RISC-V processor verification
Working draft of the proposed RISC-V V vector extension
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
lean & mean status/tabline for vim that's light as air
🔄 mpv player 播放器折腾记录 windows conf ； 中文注释配置 快速帮助入门 ； mpv-lazy 懒人包 win10 x64 config
TeachYourselfCS 的中文翻译 | A Chinese translation of TeachYourselfCS
ShellCheck, a static analysis tool for shell scripts
MyDesign.v contains the main design which was designed and then, synthesized.
Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database
GNU toolchain for RISC-V, including GCC
RISC-V Tools (ISA Simulator and Tests)
FPGA Project for EECS 151/251A (Fall 2021)
automatic-verilog based on vimscript
《Effective Modern C++》- 完成翻译
v2ray linux GUI客户端，支持订阅、vemss、ss等协议，自动更新订阅、检查版本更新
Range-Azimuth-Doppler Based Radar Object Detection