Stars
This repository presents the IC design of a 4-Bit Linear Feedback Shift Register (LFSR) also known as Pseudo Random Binary Sequence Generator; on 90nm CMOS technology.
A simple 8 bit UART implementation in Verilog, with tests and timing diagrams
Complete design of USART interface with baud rate selection
Simple 8-bit UART realization on Verilog HDL.
Universal Asynchronous Receiver-Transmitter (UART) module for serial data communication.
This repository explores efficient matrix multiplication on FPGA hardware. Communication between the PC and FPGA is implemented through UART.
基于pytorch，spikingjelly实现SNN训练MNIST手写数据集
It contains 3 different implementations of SNN using 3 different loss functions .(cross entropy , online triplet loss , offline triplet loss)
Using SNN to simulate and train neurons to see their behavior (winner takes all) to classify existing datasets like MNIST.
Spiking Neural Network RTL Implementation
Must-have verilog systemverilog modules
You can find the documents, assignments and projects of some of the courses given in Electronics and Communication engineering at Istanbul Technical University here.