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Space Invaders implementation on iCEBreaker FPGA development board

SystemVerilog 2 1 Updated Mar 21, 2023
SystemVerilog 2 Updated Oct 11, 2023
SystemVerilog 3 Updated Oct 30, 2023

CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional cache…

SystemVerilog 394 292 Updated Jun 30, 2025
Jupyter Notebook 11 Updated Nov 19, 2022

BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade

C++ 34 23 Updated Jun 17, 2025

BaseJump STL: A Standard Template Library for SystemVerilog

SystemVerilog 584 107 Updated Jun 12, 2025

LaTeX class file for writing dissertations at UC San Diego

TeX 106 65 Updated Jun 4, 2021

Parallel Programming for FPGAs -- An open-source high-level synthesis book

TeX 840 150 Updated Jan 13, 2025

Yosys Open SYnthesis Suite

C++ 3,902 971 Updated Jul 5, 2025
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