don't know the value of args of 'emitSystemVerilog' #3587
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Rogerskelamen
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You can also use the simpler version, including an option for the folder:
emitVerilog(new Add(), Array("--target-dir", "generated”))
Cheers,
Martin
… On 19.10.2023, at 13:10, RO ***@***.***> wrote:
I know that if I want to generate verilog file for my chisel code, I have to use circt.stage.ChiselStage.emitSystemVerilog. I also notice that it accepts a argument call 'args' according to the source code <https://github.com/chipsalliance/chisel/blob/86b2a7d3f7807ca0d1d8a725bd87ee4be1f61007/src/main/scala/circt/stage/ChiselStage.scala#L192>, but I don't know any available arguments I can use, so anybody helps me here?
Currently I just want to use 'args' to specify the directory that verilog code generates out.
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I know that if I want to generate verilog file for my chisel code, I have to use circt.stage.ChiselStage.emitSystemVerilog. I also notice that it accepts a argument call 'args' according to the source code, but I don't know any available arguments I can use, so anybody helps me here?
Currently I just want to use 'args' to specify the directory that verilog code generates out.
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