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Error in Build of Predefined examples of Zephyr

#69

· ayusdixit opened

on Jan 31, 2024

May I ask how to generate the build. h file used for FPGA project？

#68

· yaanng2022 opened

on Nov 27, 2023

Assertion error when running fusesoc simulation

#67

· MoonisAmir10 opened

on Aug 29, 2023

Error when building Zephyr example

#63

· aleksaj-vtool opened

on Jan 30, 2023

Read access stops when read/write access is repeated

#59

· yafuru0 opened

on Dec 26, 2022

Tested/Implemented on other cores

#58

· geoalx opened

on Dec 3, 2022

axi/wb bus cycle times

#55

· jamesbbecker opened

on Jun 27, 2022

Investigating cache performance with burst wrap reads

#52

· jeras opened

on Dec 21, 2021

fusesoc run --target=basys3 with vivado 2021.2

#51

· kendallgreen opened

on Nov 16, 2021

[Nexys4 DDR] Struggling to load into ICCM (address 0xEE000000)

#46

· mablinov opened

on Oct 13, 2021

ERROR: [Labtools 27-3165] End of startup status: LOW when [ run --target=nexys_a7 --flag=cpu_el2 swervolf]

#43

· nicolast0604 opened

on Sep 23, 2021

fusesoc run --target=sim swervolf with Verilator=3.918

#40

· nicolast0604 opened

on Jul 22, 2021

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