A comprehensive Python library for RTL (Register Transfer Level) hardware design manipulation, providing utilities for HDL abstraction, code generation, simulation, and analysis. The library bridges the gap between high-level Python programming and low-level hardware description languages.
- HDL Intermediate Representation (hdltools.abshdl.*) - Language-agnostic hardware representation
- Verilog Code Generator (hdltools.verilog.codegen) - Complete Verilog output from IR
- VHDL Code Generator (hdltools.vhdl.codegen) - Complete VHDL output from IR with functional equivalence validation
- Dual-Language Support - Generate both Verilog and VHDL from the same source
- Python HDL Syntax (hdltools.abshdl.highlvl) - Write HDL using pure Python syntax with decorators
- Memory Map Parser (hdltools.abshdl.mmap) - TextX-based memory map description language
- AXI Slave Builder (tools/axi_slave_builder.py) - Generate AXI memory-mapped slaves
- Documentation Generator (tools/mmap_docgen.py) - Automatic markdown docs from memory maps
- VCD Parser/Generator (hdltools.vcd) - Complete VCD file parsing and generation
- Cross-Language VCD Comparison (hdltools.vcd.compare) - Compare Verilog vs VHDL simulation outputs
- Hierarchy Analysis (hdltools.vcd) - VCD scope analysis and signal tracking
- Pattern Matching (hdltools.vcd, hdltools.pattern) - Temporal value pattern detection
- Event Tracking - Dynamic event monitoring with callbacks and statistics
- Hybrid Simulation (hdltools.sim.*) - Objects can be both simulated and compiled to HDL
- HDL Compiler (hdltools.sim.hdl) - AST-based Python-to-HDL conversion
- Functional Equivalence Testing - Automated validation that Verilog and VHDL produce identical results
- Verilog Parser (hdltools.verilog.parser) - Module declaration parsing
- Vector Generator (hdltools.vecgen, tools/vgc) - DSL/compiler for testbench input generation
- HDL Patterns (hdltools.hdllib.patterns) - Common HDL design patterns
- AXI Memory-Mapped Models (hdltools.hdllib.aximm) - AXI slave models using IR
- LaTeX Documentation (hdltools.latex.*) - Module block diagram generation
The library includes 8 command-line tools for various HDL and verification tasks:
axi_slave_builder- Generate AXI memory-mapped slaves from specificationsmmap_docgen- Create documentation from memory map descriptionsvgc- Vector generation compiler for test input creationvcdtracker- Value pattern tracking in VCD filesvcdhier- VCD hierarchy exploration and analysisvcdevts- Event counting and analysis from VCD filesinputgen- Test vector generation from JSON configurationsfnboundary- Function boundary detection from assembly dumps