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Python 41 5 Updated Nov 3, 2024

[ICLR2021 Outstanding Paper] Rethinking Architecture Selection in Differentiable NAS

Python 105 13 Updated Jan 5, 2022

Differentiable architecture search for convolutional and recurrent networks

Python 3,958 837 Updated Jan 3, 2021

A simple and effective LLM pruning approach.

Python 746 102 Updated Aug 9, 2024

Code for the ICML 2023 paper "SparseGPT: Massive Language Models Can Be Accurately Pruned in One-Shot".

Python 793 102 Updated Aug 20, 2024

一个基于 Android 调试 API + 百度地图实现的虚拟定位工具,并且同时实现了一个可以自由移动的摇杆

Java 7,175 823 Updated May 7, 2025

OpenSource HummingBird RISC-V Software Development Kit

C 155 51 Updated Dec 5, 2023

Nuclei RISC-V Software Development Kit

C 137 55 Updated May 8, 2025

The RIFFA development repository

Verilog 828 328 Updated Jun 11, 2024

Source files for SiFive's Freedom platforms

Scala 1,123 284 Updated Jul 17, 2021

This is the top-level project for the PULP Platform. It instantiates a PULP open-source system with a PULP SoC (microcontroller) domain accelerated by a PULP cluster with 8 cores.

SystemVerilog 490 117 Updated Nov 26, 2024

An open-source, customizable intermediate logic textbook

TeX 1,156 250 Updated Mar 29, 2025

LLM inference in C/C++

C++ 80,166 11,740 Updated May 14, 2025

Python-based Hardware Design Processing Toolkit for Verilog HDL

Python 709 197 Updated Jun 15, 2024

🚀 A simple way to launch, train, and use PyTorch models on almost any device and distributed configuration, automatic mixed precision (including fp8), and easy-to-configure FSDP and DeepSpeed support

Python 8,713 1,103 Updated May 14, 2025

本项目旨在分享大模型相关技术原理以及实战经验(大模型工程化、大模型应用落地)

HTML 17,319 2,028 Updated May 1, 2025

Digital timing diagram editor

JavaScript 999 166 Updated Jan 29, 2025

[ICML'21 Oral] I-BERT: Integer-only BERT Quantization

Python 246 36 Updated Jan 29, 2023

IC design and development should be faster,simpler and more reliable

Verilog 1,928 582 Updated Dec 31, 2021

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Assembly 2,461 766 Updated May 14, 2025

PicoRV32 - A Size-Optimized RISC-V CPU

Verilog 3,479 822 Updated Jun 27, 2024

A very simple and easy to understand RISC-V core.

C 1,230 212 Updated Nov 9, 2023

Yosys Open SYnthesis Suite

C++ 3,803 940 Updated May 14, 2025

An extremely fast Python package and project manager, written in Rust.

Rust 54,112 1,520 Updated May 14, 2025

OpenCompass is an LLM evaluation platform, supporting a wide range of models (Llama3, Mistral, InternLM2,GPT-4,LLaMa2, Qwen,GLM, Claude, etc) over 100+ datasets.

Python 5,340 566 Updated May 14, 2025

A flexible tool for creating, organizing, and sharing visualizations of live, rich data. Supports Torch and Numpy.

Python 10,135 1,144 Updated May 30, 2024

Code Repository of Evaluating Quantized Large Language Models

Python 123 6 Updated Sep 8, 2024

CUDA Templates for Linear Algebra Subroutines

C++ 7,481 1,224 Updated May 13, 2025

Development repository for the Triton language and compiler

MLIR 15,554 1,977 Updated May 14, 2025

使用 VSCode 舒适地开发 Verilog

30 3 Updated Aug 11, 2020
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