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arch/arm/rp23xx: update USB PLL/VCO/FBDIV #16300
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@keever50 if I am not mistaken you had some USB issues, could you test this changes to see any improvements. |
@shtirlic Interesting! Good catch. Ill look into this later. Yesterday I was looking at the clocks of RP2040. I have a theory that incorrect clocking or incorrect voltages cause overall instability. I hope this solves some of the USB CDC ACM serial issues. They are extremely unreliable on RP2040. (After filling the memory with enough things, more than just the nsh) I will test this later today, thank you for experimenting! |
@keever50 in pico-sdk they use the same config for USB pll for rp2040 and 2350, so you could try to change it, even set it higher for tests. |
@keever50 I am in the process of reviewing all peripherals code for rp2350 and found some of them are broken from the start due to some changes, see my pwm and watchdog current pull . Also there are some erratas and changes upstream. |
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RP2350 datasheet and upstream pico-sdk suggests higher VCO freq to better output stability. Increase the VCO and update PLL divs according to specs and calculation. Higher VCO freq is more stable, lower VCO freq is more power friendly. Also it's possible to use 120/6/5 with VCO 1440MHz for USB PLL to even higher output stability. USB setup changes from rp2040 Must clear the MAIN_CTRL.PHY_ISO bit at startup and after power down events. Signed-off-by: Serg Podtynnyi <serg@podtynnyi.com>
@cederom what's problem make the merge button gray? |
@xiaoxiang781216 maybe because of this, I asked @acassis to re-approve to see if it helps
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the problem now change to build/check never finish. |
@shtirlic try rebase to last master |
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Thank you @shtirlic :-)
Sorry for the problems we are updating PR merge rules and in a short window of testing we will update all settings as needed :-) |
@cederom what does it mean "Waiting for status to be reported" ? |
Allright the PR processing is now fixed, merging :-) |
Summary
RP2350 datasheet and upstream pico-sdk suggests higher VCO freq to
better output stability.
Increase the VCO and update PLL divs according to specs and calculation.
Higher VCO freq is more stable, lower VCO freq is more power friendly.
Also it's possible to use 120/6/5 with VCO 1440MHz for USB PLL to even
higher output stability.
USB setup changes from rp2040
Must clear the MAIN_CTRL.PHY_ISO bit at startup and after power down
events.
Impact
More stable USB operations
Testing