Lists (3)
Stars
A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education and research.
A LaTeX beamer theme template for CQU students.
Comprehensive tools and frameworks for developing foundation models tailored to recommendation systems.
在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。
Dream-my-heart / NPU_on_FPGA
Forked from cxdzyq1110/NPU_on_FPGA在FPGA上面实现一个NPU计算单元。能够执行矩阵运算（ADD/ADDi/ADDs/MULT/MULTi/DOT等）、图像处理运算（CONV/POOL等）、非线性映射（RELU/TANH/SIGM等）。
An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). 基于FPGA的GZIP压缩器。输入原始数据，输出标准的GZIP格式，即常见的 .gz / .tar.gz 文件的格式。
A highly optimized LLM inference acceleration engine for Llama and its variants.
Github Pages template based upon HTML and Markdown for personal, portfolio-based websites.
Implementation of Denoising Diffusion Probabilistic Model in Pytorch
A “Toy” Script transoforms MLIR Affine Dialect to Dot Visualized Format
This Repo describle the hardware description of MDC in Chiesl hardware language
🌊 Digital timing diagram rendering engine
This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clock domains and time-shared design
分享FPGA开发知识、优秀文章、学习网站以及开源项目。本项目收集了github中许多FPGA开源项目。
Fourier ACelerator Compiler Framework. Efforts have been taken to blind code for submission.
DO NOT CHECK OUT THESE FILES FROM GITHUB UNLESS YOU KNOW WHAT YOU ARE DOING. (See below.)
An Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation
Allo: A Programming Model for Composable Accelerator Design
重庆大学视觉标识素材包 --- Visual Identification Bundle of Chongqing University