Stars
Digital timing diagram editor
OS Summer of Code 2020 每日学习实践记录（rust 学习 & rcore tutorial rust实现一个riscv操作系统 & rCore 到 zCore 的功能迁移）
The LLVM Project is a collection of modular and reusable compiler and toolchain technologies.
Project moved to: https://github.com/llvm/llvm-project
RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
An Open-Source Design and Verification Environment for RISC-V
An environment for building LiteX based FPGA designs. Makes it easy to get everything you need!
CoreMark® is an industry-standard benchmark that measures the performance of central processing units (CPU) and embedded microcrontrollers (MCU).
HDLBits website practices & solutions
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
A simple, basic, formally verified UART controller
Verilog AXI components for FPGA implementation
Small footprint and configurable PCIe core
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
A Scala library for Context-Dependent Environments
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
CVA6 SDK containing RISC-V tools and Buildroot
SCR1 is a high-quality open-source RISC-V MCU core in Verilog
Antmicro's fast, vendor-neutral DMA IP in Chisel
This sample is the end product for the walkthrough on https://docs.microsoft.com/en-us/visualstudio/python/working-with-c-cpp-python-in-visual-studio
Must-have verilog systemverilog modules