Final Project for ECE243 where I created a Computer with a CPU, Memory and I/O on the DE1-SOC FPGA using Verilog.
The given code, when compiled using code/IO.v will run the program lab1.txt and lab2_big.txt when either KEY1 or KEY2 is pressed in combination with KEY0 (reset).
- lab1
- Adds up numbers from 1 to 30 and places result in R4
- lab2
- Search through list and place biggest element in R4
You can then use SW[2:0] to set which register you want to look at, in the RegisterFile, and the output will be displayed on HEX0-3 in hexadecimal.
If you want to run other programs on the FPGA, update code/memory.v with the output of compiler/output.txt after running the compiler/compiler.py script on your input file.
The compiler.py file allows for easy compilation of your assembly code into machine code.
To use it:
- Create a new ".txt" file in the compiler folder and write your code in there
- Go to compiler.py and change input_file in line 1 to the name of your ".txt" file
- Run the script. Your machine code will be found in output.txt
- Copy code from output.txt to memory.v in line 24
The compiler allows for:
- a "data" section
- can put stuff into memory to start
- a "code" section
- write your code here
- comments
- use # to write comments
- empty lines
- parser automatically skips empty lines
for more details go to example.txt.
Description of the assembly language used for this processor. It is similar to NIOS II.
Arithmetic instructions follow this format: XXX Rout Ra Rb. You can do the following operations:
- ADD
- SUB
- OR
- AND
- XOR
- SL (shift left logic)
- SR (shift right logic)
Arithmetic Immediate instructions follow this format: XXX Rout Ra Immed5. Immed5 can be a decimal or binary, but for binary, must write "0b" before number (i.e. 0b11, 0b11011). You can do the following operations:
- ADDI
- SUBI
- ORI
- ANDI
- XORI
- SLI (shift left logic)
- SRI (shift right logic)
Comparison instructions follow this format: XXX Rout Ra Rb. You can do the following operations:
- GT (Ra > Rb)
- LT (Ra < Rb)
- EQ (Ra == Rb)
Branch instructions follow this format: XXX Immed5. You can do the following operations:
- BR (normal branch)
- BRZ (branch if Z flag is 1, meaning last operations in ALU was equal to 0)
Load instructions follow this format: XXX Rout, (Ra). (Rout = *Ra)
Store instructions follow this format: XXX Rb, (Ra). (*Ra = Rb)