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    299 repositories

    • ara

      Public
      The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core
      asiccpuvectorriscvararvvrv64gcv
      C
      •
      Other
      •138•401•70•5•Updated Mar 4, 2025Mar 4, 2025

    • croc

      Public
      A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
      asicriscvsystemverilogrtl-design
      SystemVerilog
      •
      Other
      •9•58•1•2•Updated Mar 4, 2025Mar 4, 2025

    • chimera-sdk

      Public
      C
      •
      Apache License 2.0
      •4•3•7•4•Updated Mar 4, 2025Mar 4, 2025

    • redmule

      Public
      SystemVerilog
      •
      Other
      •13•45•1•3•Updated Mar 4, 2025Mar 4, 2025

    • astral

      Public
      A space computing platform built around Cheshire, with a configurable number of safety, security, reliability and predictability features with a ready-to-use FPGA flow on multiple boards.
      cfpgaspaceacceleratorriscvsystemverilogmulticoresafety-criticalheterogeneous-computing
      Tcl
      •
      Other
      •16•6•0•6•Updated Mar 4, 2025Mar 4, 2025

    • cva6-sdk

      Public
      CVA6 SDK containing RISC-V tools and Buildroot
      Makefile
      •68•1•0•2•Updated Mar 4, 2025Mar 4, 2025

    • opensbi

      Public
      RISC-V Open Source Supervisor Binary Interface
      C
      •
      Other
      •546•0•0•2•Updated Mar 4, 2025Mar 4, 2025

    • spatz

      Public
      Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
      C
      •
      Apache License 2.0
      •21•95•1•3•Updated Mar 4, 2025Mar 4, 2025

    • cheshire

      Public
      A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
      asicriscvsystemverilogrtl-designfpgasimulation
      Verilog
      •
      Other
      •54•229•10•19•Updated Mar 3, 2025Mar 3, 2025

    • cva6

      Public
      This is the fork of CVA6 intended for PULP development.
      Assembly
      •
      Other
      •731•19•0•5•Updated Mar 3, 2025Mar 3, 2025

    • chimera

      Public
      Python
      •
      Other
      •3•15•9•3•Updated Feb 28, 2025Feb 28, 2025

    • picobello

      Public
      whatever it means
      SystemVerilog
      •
      Other
      •0•5•7•0•Updated Feb 28, 2025Feb 28, 2025

    • iDMA

      Public
      A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
      SystemVerilog
      •
      Other
      •29•128•7•1•Updated Feb 28, 2025Feb 28, 2025

    • FlooNoC

      Public
      A Fast, Low-Overhead On-chip Network
      SystemVerilog
      •
      Apache License 2.0
      •30•179•15•5•Updated Feb 28, 2025Feb 28, 2025

    • common_cells

      Public
      Common SystemVerilog components
      SystemVerilog
      •
      Other
      •156•579•31•9•Updated Feb 28, 2025Feb 28, 2025

    • pulp_cluster

      Public
      The multi-core cluster of a PULP system.
      SystemVerilog
      •
      Other
      •23•73•5•3•Updated Feb 27, 2025Feb 27, 2025

    • axi

      Public
      AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
      asicfpgahardwarertlipsystemverilogaxinetwork-on-chipaxi4axi4-lite
      SystemVerilog
      •
      Other
      •278•1.2k•45•9•Updated Feb 27, 2025Feb 27, 2025

    • Deeploy

      Public
      DNN Compiler for Heterogeneous SoCs
      mcutinymlml-compiler
      Python
      •
      Apache License 2.0
      •11•26•8•4•Updated Feb 27, 2025Feb 27, 2025

    • InjectaFault

      Public
      Tcl
      •
      Other
      •2•6•0•0•Updated E30A Feb 27, 2025Feb 27, 2025

    • artistic

      Public
      An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders
      asicrenderinggdsii
      Python
      •
      Apache License 2.0
      •1•12•0•0•Updated Feb 27, 2025Feb 27, 2025

    • axi_llc

      Public
      SystemVerilog
      •
      Other
      •15•23•3•5•Updated Feb 27, 2025Feb 27, 2025

    • mempool

      Public
      A 256-RISC-V-core system with low-latency access into shared L1 memory.
      asicrisc-vmanycore
      C
      •
      Apache License 2.0
      •47•285•3•5•Updated Feb 27, 2025Feb 27, 2025

    • eae-kws

      Public
      Python
      •
      Apache License 2.0
      •0•0•0•0•Updated Feb 26, 2025Feb 26, 2025

    • unbent

      Public
      SystemVerilog
      •
      Other
      •0•2•0•1•Updated Feb 26, 2025Feb 26, 2025

    • pulp-runtime

      Public
      Simple runtime for Pulp platforms
      C
      •36•42•7•4•Updated Feb 25, 2025Feb 25, 2025

    • regression_tests

      Public
      C
      •17•8•3•1•Updated Feb 25, 2025Feb 25, 2025

    • hci

      Public
      Heterogeneous Cluster Interconnect to bind special-purpose HW accelerators with general-purpose cluster cores
      SystemVerilog
      •
      Other
      •11•12•4•3•Updated Feb 25, 2025Feb 25, 2025

    • u-boot

      Public
      Unofficial development fork of U-Boot
      C
      •12•0•0•1•Updated Feb 25, 2025Feb 25, 2025

    • pulp-nnx

      Public
      C
      •
      Apache License 2.0
      •0•4•0•0•Updated Feb 25, 2025Feb 25, 2025

    • hwpe-stream

      Public
      IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system
      SystemVerilog
      •
      Other
      •19•19•2•3•Updated Feb 24, 2025Feb 24, 2025
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