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    61 repositories

    • cva5

      Public
      The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
      SystemVerilog
      •
      Apache License 2.0
      •27•102•4•0•Updated May 15, 2025May 15, 2025

    • cvw-arch-verif

      Public
      The purpose of the repo is to support CORE-V Wally architectural verification
      SystemVerilog
      •
      Other
      •32•11•26•2•Updated May 15, 2025May 15, 2025

    • cva6

      Public
    The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
    asiccpusystemverilog-hdlrv64gcarianefpgarisc-v
    Assembly
    •
    Other
    •766•2.5k•192•12•Updated May 15, 2025May 15, 2025

  • cvw

    Public
    CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
    SystemVerilog
    •
    Other
    •285•374•27•7•Updated May 14, 2025May 14, 2025

  • core-v-verif

    Public
    Functional verification project for the CORE-V family of RISC-V cores.
    verificationsystemveriloguvmrisc-v
    Assembly
    •
    Other
    •238•534•130•14•Updated May 8, 2025May 8, 2025

  • core-v-mcu

    Public
    This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
    microcontrollerriscvsystemverilogopenhwgroup
    SystemVerilog
    •
    Other
    •61•176•73•5•Updated May 1, 2025May 1, 2025

  • tristan-isolde-unified-access-page

    Public
    Unified Access Page for the TRISTAN project
    HTML
    •34•16•2•2•Updated Apr 24, 2025Apr 24, 2025

  • osdforum.org

    Public
    The Open Source Developer Forum is a workshop that brings open source software and hardware (chips, boards and systems) developers together to collaborate and learn.
    webdevhugo
    HTML
    •
    Eclipse Public License 2.0
    •6•1•0•0•Updated Apr 22, 2025Apr 22, 2025

  • cv-hpdcache

    Public
    RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
    SystemVerilog
    •
    Other
    •30•72•5•0•Updated Apr 18, 2025Apr 18, 2025

  • programs

    Public
    Documentation for the OpenHW Group's set of CORE-V RISC-V cores
    HTML
    •
    Other
    •98•212•9•11•Updated Apr 10, 2025Apr 10, 2025

  • cve2

    Public
    The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
    SystemVerilog
    •
    Apache License 2.0
    •602•42•156•11•Updated Apr 10, 2025Apr 10, 2025

  • openhwgroup.org

    Public
    OpenHW Group is a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. OpenHW provides an infrastructure for hosting high quality open-source HW developments in line with industry best practi…
    webdevhugo
    HTML
    •
    Eclipse Public License 2.0
    •11•18•3•3•Updated Mar 19, 2025Mar 19, 2025

  • cv32e20-dv

    Public
    Assembly
    •
    Apache License 2.0
    •9•1•0•2•Updated Mar 18, 2025Mar 18, 2025

  • core-v-sw

    Public
    Main Repo for the OpenHW Group Software Task Group
    Eclipse Public License 2.0
    •28•17•6•0•Updated Mar 11, 2025Mar 11, 2025

  • cv-mesh

    Public
    Verilog
    •0•3•0•0•Updated Mar 10, 2025Mar 10, 2025

  • core-v-cores

    Public
    CORE-V Family of RISC-V Cores
    17•266•1•0•Updated Feb 13, 2025Feb 13, 2025

  • cv32e40p

    Public
    CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
    riscvriscv32imfc
    SystemVerilog
    •
    Other
    •450•1.1k•50•11•Updated Feb 12, 2025Feb 12, 2025

  • cv-hpdcache-verif

    Public
    Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.
    SystemVerilog
    •
    Apache License 2.0
    •4•11•0•0•Updated Feb 12, 2025Feb 12, 2025

  • cvfpu

    Public
    Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
    SystemVerilog
    •
    Apache License 2.0
    •130•489•39•11•Updated Feb 12, 2025Feb 12, 2025

  • cv32e40s-dv

    Public
    CV32E40S Design-Verification environment
    Assembly
    •
    Apache License 2.0
    •1•0•1•0•Updated Nov 11, 2024Nov 11, 2024

  • cv32e40x

    Public
    4 stage, in-order, compute RISC-V core based on the CV32E40P
    SystemVerilog
    •
    Other
    •52•237•31•5•Updated Nov 6, 2024Nov 6, 2024

  • cv32e40s

    Public
    4 stage, in-order, secure RISC-V core based on the CV32E40P
    SystemVerilog
    •
    Other
    •24•146•2•2•Updated Oct 31, 2024Oct 31, 2024

  • corev-qemu

    Public
    Official QEMU mirror. Please see http://wiki.qemu.org/Contribute/SubmitAPatch for how to submit changes to QEMU. Pull Requests are ignored. Please only use release tarballs from the QEMU website.
    C
    •
    Other
    •5.9k•1•0•2•Updated Aug 16, 2024Aug 16, 2024

  • core-v-polara-apu

    Public
    The OpenPiton Platform
    Assembly
    •237•16•0•2•Updated Aug 14, 2024Aug 14, 2024

  • corev-binutils-gdb

    Public
    C
    •
    GNU General Public License v2.0
    •26•9•4•0•Updated Jul 30, 2024Jul 30, 2024

  • corev-llvm-project

    Public
    Other
    •18•13•4•2•Updated Jul 26, 2024Jul 26, 2024

  • core-v-mcu-uvm

    Public
    CORE-V MCU UVM Environment and Test Bench
    SystemVerilog
    •
    Other
    •8•21•16•0•Updated Jul 19, 2024Jul 19, 2024

  • corev-gcc

    Public
    C++
    •
    GNU General Public License v2.0
    •23•23•8•1•Updated Jul 19, 2024Jul 19, 2024

  • cva6-sdk

    Public
    CVA6 SDK containing RISC-V tools and Buildroot
    Makefile
    •77•66•33•4•Updated Jun 22, 2024Jun 22, 2024

  • core-v-xif

    Public
    RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
    SystemVerilog
    •
    Other
    •27•65•19•1•Updated May 22, 2024May 22, 2024
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