8000 olofk (Olof Kindgren) / Starred · GitHub
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BitBake 1 4 Updated Dec 12, 2024

Recent updates and features added to the RVfpga course developed by Imagination Technologies.

C 16 2 Updated Jun 16, 2025

Minimal SoC containing a Serv-RV32I Core designed for usage with Liberty74

Verilog 2 Updated Jun 2, 2024
88F6

An abstraction library for interfacing EDA tools

Python 696 203 Updated Jun 16, 2025

Small SERV-based SoC primarily for OpenMPW tapeout

Verilog 43 12 Updated Jun 4, 2025

Package manager and build abstraction tool for FPGA/ASIC development

Python 1,300 260 Updated Jun 19, 2025

SERV - The SErial RISC-V CPU

Verilog 1,602 220 Updated Jun 5, 2025

A collection of core generators to use with FuseSoC

Python 16 12 Updated Aug 23, 2024

FuseSoC standard core library

143 37 Updated May 26, 2025

Example LED blinking project for your FPGA dev board of choice

Tcl 177 74 Updated May 26, 2025

FOSSi Foundation Website

HTML 1 Updated Mar 19, 2020

FuseSoC-based SoC for VeeR EH1 and EL2

Verilog 320 73 Updated Dec 11, 2024

mor1kx - an OpenRISC 1000 processor IP core

Verilog 546 150 Updated Mar 29, 2025
Python 1 Updated Aug 19, 2016
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