Automated ASIC and FPGA design for Tsetlin Machine Acclerators. The repo is organized according to the table below:
| Repo Branch | Description |
|---|---|
main |
Used to give an overview of each Matador flow branch. |
development |
Branch for automated FPGA accelerator design. |
Contributors: Tousif Rahman, Gang Mao, Sidharth Maheshwari, Marcos Sartori, Shengyu Duan, Bob Pattison