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Tri-mode (10/100/1000) full-duplex FPGA ethernet MAC in VHDL
VUnit is a unit testing framework for VHDL/SystemVerilog
Generate Rust register maps (`struct`s) from SVD files
🎛 A Svelte library for building dynamic, infinitely customizable node-based user interfaces and flowcharts
A low profile split keyboard designed to satisfy one single use case elegantly
Real-Time Interrupt-driven Concurrency (RTIC) framework for ARM Cortex-M microcontrollers