-
emacs-resources Public
emacs config, with out use package install for some mechine not has internet for package install
Emacs Lisp UpdatedMar 4, 2025 -
-
-
RTL---DEVEL_Learn_Bluespec_and_RISCV_Design Public
Forked from rsnikhil/DEVEL_Learn_Bluespec_and_RISCV_DesignDevelopment area for another repo: Learn_Bluespec_and_RISCV_Design
Bluespec UpdatedDec 18, 2024 -
verilog-ext Public
Forked from gmlarumbe/verilog-extVerilog Extensions for Emacs
Emacs Lisp GNU General Public License v3.0 UpdatedNov 30, 2024 -
axi Public
Forked from pulp-platform/axiAXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
SystemVerilog Other UpdatedNov 30, 2024 -
RTL-design-RISCV-BSV-refer-Toooba Public
Forked from bluespec/TooobaRISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT
Verilog Other UpdatedNov 30, 2024 -
RTL---BSV-BlueAXI Public
Forked from esa-tu-darmstadt/BlueAXIBluespec MIT License UpdatedNov 25, 2024 -
Learn_Bluespec_and_RISCV_Design Public
Forked from rsnikhil/Learn_Bluespec_and_RISCV_DesignTextbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
Verilog MIT License UpdatedSep 13, 2024 -
RTL---blue-rdma Public
Forked from datenlord/blue-rdmaRoCEv2 hardware implementation in Bluespec SystemVerilog
Bluespec GNU General Public License v2.0 UpdatedSep 12, 2024 -
RTL-design-hdl-reference Public
Forked from analogdevicesinc/hdlHDL libraries and projects
Verilog Other UpdatedSep 6, 2024 -
RTL-tools-perl-HDLGen Public
Forked from WilsonChen003/HDLGenHDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded functions, with ZERO learning-curve
Verilog UpdatedAug 18, 2024 -
RTL---tiny-gpu Public
Forked from adam-maj/tiny-gpuA minimal GPU design in Verilog to learn how GPUs work from the ground up
SystemVerilog UpdatedAug 18, 2024 -
RTL-language-BSV-BSV_Tutorial_cn Public
Forked from WangXuan95/BSV_Tutorial_cn爆肝6万字的 Bluespec SystemVerilog (BSV) 中文教程
Bluespec GNU General Public License v3.0 UpdatedAug 17, 2024 -
RTL-tools-language-bsc Public
Forked from B-Lang-org/bscBluespec Compiler (BSC)
Haskell Other UpdatedMay 15, 2024 -
py-economy-trader Public
Forked from BigBrotherTrade/trader交易模块
Python Apache License 2.0 UpdatedMay 13, 2024 -
cpp_etudes_calltree Public
Forked from satanson/cpp_etudessmart tools for source code study : cpptree.pl, calltree.pl, javatree.pl, java_calltree.pl
C++ UpdatedMay 11, 2024 -
RTL-lib-common_cells Public
Forked from pulp-platform/common_cellsCommon SystemVerilog components
SystemVerilog Other UpdatedMay 4, 2024 -
hello-algo Public
Forked from krahets/hello-algo《Hello 算法》：动画图解、一键运行的数据结构与算法教程，支持 Python, C++, Java, C#, Go, Swift, JS, TS, Dart, Rust, C, Zig 等语言。English edition ongoing
Java Other UpdatedApr 6, 2024 -
RTL-tinyriscv Public
Forked from liangkangnan/tinyriscvA very simple and easy to understand RISC-V core.
C Apache License 2.0 UpdatedNov 9, 2023 -
ventus-gpgpu Public
Forked from THU-DSP-LAB/ventus-gpgpuGPGPU processor supporting RISCV-V extension, developed with Chisel HDL
Scala Other UpdatedOct 27, 2023 -
RTL-tools-vim-automatic-verilog Public
Forked from HonkW93/automatic-verilogautomatic-verilog based on vimscript
Vim Script GNU General Public License v3.0 UpdatedSep 2, 2023 -
RTL-tools-vim-verilog_systemverilog.vim Public
Forked from vhda/verilog_systemverilog.vimVerilog/SystemVerilog Syntax and Omni-completion
Vim Script UpdatedSep 2, 2023 -
RTL---Self_Attention_Accelerator Public
Forked from Vishnu2912/Self_Attention_AcceleratorHardware Accelerator for Self Attention Layer in Bluespec - for Shakti C Class
Bluespec UpdatedJun 1, 2023 -
AI---hands-on-ml-2e-zh Public
Forked from apachecn-archive/hands-on-ml-2e-zhCSS UpdatedMay 3, 2023 -
RTL-design-RISCV-BSV-refer-Flute Public
Forked from bluespec/FluteRISC-V CPU, simple 5-stage in-order pipeline, for low-end applications needing MMUs and some performance
Bluespec Apache License 2.0 UpdatedApr 29, 2023 -
RTL-tools-emacs-verilog-mode Public
Forked from veripool/verilog-modeVerilog-Mode for Emacs with Indentation, Hightlighting and AUTOs. Master repository for pushing to GNU, verilog.com and veripool.org.
SystemVerilog GNU General Public License v3.0 UpdatedMar 1, 2023 -
RTL---MIT_Bluespec_RISCV_Tutorial Public
Forked from adamgallas/MIT_Bluespec_RISCV_TutorialC UpdatedJan 22, 2023 -
RTL-design-riscv-e203_hbirdv2 Public
Forked from riscv-mcu/e203_hbirdv2The Ultra-Low Power RISC-V Core
Verilog Apache License 2.0 UpdatedFeb 24, 2022 -
RTL-designs-RISCV-BSV-refer-Piccolo Public
Forked from bluespec/PiccoloRISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
Verilog Apache License 2.0 UpdatedJan 23, 2022
{{ message }}