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Synchronization-aware Trace Replay for gem5 simulation speed up
Dynamic ControlFlow Graph and DataFlow Graph for Binary-based Optimization
HME a hybrid memory emulator for studying the performance and energy characteristics of upcoming NVM technologies. HME exploits features available in commodity NUMA architectures to emulate two kin…
cluster data collected from production clusters in Alibaba for cluster management research
Trying to figure various CPU things out
ASM methods to test small loop performance on x86
Measures the latency between CPU cores
The micro-benchmark suite to evaluate the micro-architecture of China's home-grown many-core processor SW26010
Benchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 paper: Ghose et al., "Demystifying Complex Workload-DRAM Int…
zhenman / MemBen
Forked from CMU-SAFARI/MemBenBenchmark suite containing cache filtered traces for use with Ramulator. These include some of the workloads used in our SIGMETRICS 2019 paper: Ghose et al., "Demystifying Complex Workload-DRAM Int…
[FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers
ChampSim is an open-source trace based simulator maintained at Texas A&M University and through the support of the computer architecture community.
ELF file viewer/editor for Windows, Linux and MacOS.
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This repository is a hands-on tutorial which aims at going through dissection and analysis of arbitrary binaries.
Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, T…
PrIM (Processing-In-Memory benchmarks) is the first benchmark suite for a real-world processing-in-memory (PIM) architecture. PrIM is developed to evaluate, analyze, and characterize the first publ…
Visualization tool for designing mesh Network-on-Chips (NoC) and assisting with architecture research
"Simulator" with instruction tracing and deterministic timing for x86 programs
Modified version of SimpleScalar (3.0e) for store memory access trace.
Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy